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Searched refs:SOCFPGA_PLL_DIVF_SHIFT (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/socfpga/
Dclk-pll-a10.c22 #define SOCFPGA_PLL_DIVF_SHIFT 0 macro
43 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
Dclk-pll.c27 #define SOCFPGA_PLL_DIVF_SHIFT 3 macro
51 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()