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Searched refs:SPLL_CTLREQ_CHG (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi.c1339 tmp |= SPLL_CTLREQ_CHG; in si_set_clk_bypass_mode()
1349 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE); in si_set_clk_bypass_mode()
Dsid.h98 #define SPLL_CTLREQ_CHG (1 << 23) macro
/drivers/gpu/drm/radeon/
Dsid.h97 #define SPLL_CTLREQ_CHG (1 << 23) macro
Dsi.c3995 tmp |= SPLL_CTLREQ_CHG; in si_set_clk_bypass_mode()
4005 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE); in si_set_clk_bypass_mode()