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Searched refs:SSPP_VIG1 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
117 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
205 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
457 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
676 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
Dmdp5_ctl.c293 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
316 case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3; in mdp_ctl_blend_ext_mask()
444 case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1; in mdp_ctl_flush_mask_pipe()
Dmdp5.xml.h77 SSPP_VIG1 = 2, enumerator
551 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); in __offset_PIPE()
Dmdp5_kms.c688 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c139 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; in dpu_hw_get_danger_status()
236 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_mdss.h112 SSPP_VIG1, enumerator
Ddpu_hw_ctl.c160 case SSPP_VIG1: in dpu_hw_ctl_update_pending_flush_sspp()
423 case SSPP_VIG1: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_catalog.c809 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK,
828 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
873 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,