1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9 #ifndef __HALDMOUTSRC_H__ 10 #define __HALDMOUTSRC_H__ 11 12 #include "odm_EdcaTurboCheck.h" 13 #include "odm_DIG.h" 14 #include "odm_DynamicBBPowerSaving.h" 15 #include "odm_DynamicTxPower.h" 16 #include "odm_CfoTracking.h" 17 18 #define TP_MODE 0 19 #define RSSI_MODE 1 20 #define TRAFFIC_LOW 0 21 #define TRAFFIC_HIGH 1 22 #define NONE 0 23 24 /* 3 Tx Power Tracking */ 25 /* 3 ============================================================ */ 26 #define DPK_DELTA_MAPPING_NUM 13 27 #define index_mapping_HP_NUM 15 28 #define OFDM_TABLE_SIZE 43 29 #define CCK_TABLE_SIZE 33 30 #define TXSCALE_TABLE_SIZE 37 31 #define TXPWR_TRACK_TABLE_SIZE 30 32 #define DELTA_SWINGIDX_SIZE 30 33 #define BAND_NUM 4 34 35 /* 3 PSD Handler */ 36 /* 3 ============================================================ */ 37 38 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 39 #define MODE_40M 0 /* 0:20M, 1:40M */ 40 #define PSD_TH2 3 41 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 42 #define SIR_STEP_SIZE 3 43 #define Smooth_Size_1 5 44 #define Smooth_TH_1 3 45 #define Smooth_Size_2 10 46 #define Smooth_TH_2 4 47 #define Smooth_Size_3 20 48 #define Smooth_TH_3 4 49 #define Smooth_Step_Size 5 50 #define Adaptive_SIR 1 51 #define PSD_RESCAN 4 52 #define PSD_SCAN_INTERVAL 700 /* ms */ 53 54 /* 8723A High Power IGI Setting */ 55 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 56 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 57 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 58 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 59 60 /* ANT Test */ 61 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 62 #define ANTTESTA 0x01 /* Ant A will be Testing */ 63 #define ANTTESTB 0x02 /* Ant B will be testing */ 64 65 #define PS_MODE_ACTIVE 0x01 66 67 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 68 #define MAIN_ANT 1 /* Ant A or Ant Main */ 69 #define AUX_ANT 2 /* AntB or Ant Aux */ 70 #define MAX_ANT 3 /* 3 for AP using */ 71 72 /* Antenna Diversity Type */ 73 #define SW_ANTDIV 0 74 #define HW_ANTDIV 1 75 /* structure and define */ 76 77 /* Remove DIG by Yuchen */ 78 79 /* Remoce BB power saving by Yuchn */ 80 81 /* Remove DIG by yuchen */ 82 83 struct dynamic_primary_CCA { 84 u8 PriCCA_flag; 85 u8 intf_flag; 86 u8 intf_type; 87 u8 DupRTS_flag; 88 u8 Monitor_flag; 89 u8 CH_offset; 90 u8 MF_state; 91 }; 92 93 struct ra_t { 94 u8 firstconnect; 95 }; 96 97 struct rxhp_t { 98 u8 RXHP_flag; 99 u8 PSD_func_trigger; 100 u8 PSD_bitmap_RXHP[80]; 101 u8 Pre_IGI; 102 u8 Cur_IGI; 103 u8 Pre_pw_th; 104 u8 Cur_pw_th; 105 bool First_time_enter; 106 bool RXHP_enable; 107 u8 TP_Mode; 108 struct timer_list PSDTimer; 109 }; 110 111 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 112 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 113 114 /* This indicates two different the steps. */ 115 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 116 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 117 /* with original RSSI to determine if it is necessary to switch antenna. */ 118 #define SWAW_STEP_PEAK 0 119 #define SWAW_STEP_DETERMINE 1 120 121 #define TP_MODE 0 122 #define RSSI_MODE 1 123 #define TRAFFIC_LOW 0 124 #define TRAFFIC_HIGH 1 125 #define TRAFFIC_UltraLOW 2 126 127 struct swat_t { /* _SW_Antenna_Switch_ */ 128 u8 Double_chk_flag; 129 u8 try_flag; 130 s32 PreRSSI; 131 u8 CurAntenna; 132 u8 PreAntenna; 133 u8 RSSI_Trying; 134 u8 TestMode; 135 u8 bTriggerAntennaSwitch; 136 u8 SelectAntennaMap; 137 u8 RSSI_target; 138 u8 reset_idx; 139 u16 Single_Ant_Counter; 140 u16 Dual_Ant_Counter; 141 u16 Aux_FailDetec_Counter; 142 u16 Retry_Counter; 143 144 /* Before link Antenna Switch check */ 145 u8 SWAS_NoLink_State; 146 u32 SWAS_NoLink_BK_Reg860; 147 u32 SWAS_NoLink_BK_Reg92c; 148 u32 SWAS_NoLink_BK_Reg948; 149 bool ANTA_ON; /* To indicate Ant A is or not */ 150 bool ANTB_ON; /* To indicate Ant B is on or not */ 151 bool Pre_Aux_FailDetec; 152 bool RSSI_AntDect_bResult; 153 u8 Ant2G; 154 155 s32 RSSI_sum_A; 156 s32 RSSI_sum_B; 157 s32 RSSI_cnt_A; 158 s32 RSSI_cnt_B; 159 160 u64 lastTxOkCnt; 161 u64 lastRxOkCnt; 162 u64 TXByteCnt_A; 163 u64 TXByteCnt_B; 164 u64 RXByteCnt_A; 165 u64 RXByteCnt_B; 166 u8 TrafficLoad; 167 u8 Train_time; 168 u8 Train_time_flag; 169 struct timer_list SwAntennaSwitchTimer; 170 struct timer_list SwAntennaSwitchTimer_8723B; 171 u32 PktCnt_SWAntDivByCtrlFrame; 172 bool bSWAntDivByCtrlFrame; 173 }; 174 175 /* Remove Edca by YuChen */ 176 177 178 struct odm_rate_adaptive { 179 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 180 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 181 bool bUseLdpc; 182 bool bLowerRtsRate; 183 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 184 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 185 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 186 187 }; 188 189 #define IQK_MAC_REG_NUM 4 190 #define IQK_ADDA_REG_NUM 16 191 #define IQK_BB_REG_NUM_MAX 10 192 #define IQK_BB_REG_NUM 9 193 #define HP_THERMAL_NUM 8 194 195 #define AVG_THERMAL_NUM 8 196 #define IQK_Matrix_REG_NUM 8 197 #define IQK_Matrix_Settings_NUM 14 /* Channels_2_4G_NUM */ 198 199 #define DM_Type_ByFW 0 200 #define DM_Type_ByDriver 1 201 202 /* */ 203 /* Declare for common info */ 204 /* */ 205 #define MAX_PATH_NUM_92CS 2 206 #define MAX_PATH_NUM_8188E 1 207 #define MAX_PATH_NUM_8192E 2 208 #define MAX_PATH_NUM_8723B 1 209 #define MAX_PATH_NUM_8812A 2 210 #define MAX_PATH_NUM_8821A 1 211 #define MAX_PATH_NUM_8814A 4 212 #define MAX_PATH_NUM_8822B 2 213 214 #define IQK_THRESHOLD 8 215 #define DPK_THRESHOLD 4 216 217 struct odm_phy_info { 218 /* 219 * Be care, if you want to add any element, please insert it between 220 * rx_pwd_ball and signal_strength. 221 */ 222 u8 rx_pwd_ba11; 223 224 u8 signal_quality; /* in 0-100 index. */ 225 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 226 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 227 228 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 229 230 u16 cfo_short[4]; /* per-path's Cfo_short */ 231 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 232 233 s8 rx_power; /* in dBm Translate from PWdB */ 234 235 /* 236 * Real power in dBm for this packet, no beautification and 237 * aggregation. Keep this raw info to be used for the other procedures. 238 */ 239 s8 recv_signal_power; 240 u8 bt_rx_rssi_percentage; 241 u8 signal_strength; /* in 0-100 index. */ 242 243 s8 rx_pwr[4]; /* per-path's pwdb */ 244 245 u8 rx_snr[4]; /* per-path's SNR */ 246 u8 band_width; 247 u8 bt_coex_pwr_adjust; 248 }; 249 250 struct odm_packet_info { 251 u8 data_rate; 252 u8 station_id; 253 bool bssid_match; 254 bool to_self; 255 bool is_beacon; 256 }; 257 258 struct odm_phy_dbg_info { 259 /* ODM Write, debug info */ 260 s8 RxSNRdB[4]; 261 u32 NumQryPhyStatus; 262 u32 NumQryPhyStatusCCK; 263 u32 NumQryPhyStatusOFDM; 264 u8 NumQryBeaconPkt; 265 /* Others */ 266 s32 RxEVM[4]; 267 268 }; 269 270 struct odm_mac_status_info { 271 u8 test; 272 }; 273 274 /* */ 275 /* 2011/10/20 MH Define Common info enum for all team. */ 276 /* */ 277 enum odm_cmninfo_e { 278 /* Fixed value: */ 279 280 /* HOOK BEFORE REG INIT----------- */ 281 ODM_CMNINFO_PLATFORM = 0, 282 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 283 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 284 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 285 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 286 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 287 ODM_CMNINFO_RFE_TYPE, 288 ODM_CMNINFO_PACKAGE_TYPE, 289 ODM_CMNINFO_EXT_LNA, /* true */ 290 ODM_CMNINFO_EXT_PA, 291 ODM_CMNINFO_GPA, 292 ODM_CMNINFO_APA, 293 ODM_CMNINFO_GLNA, 294 ODM_CMNINFO_ALNA, 295 ODM_CMNINFO_EXT_TRSW, 296 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 297 ODM_CMNINFO_BINHCT_TEST, 298 ODM_CMNINFO_BWIFI_TEST, 299 ODM_CMNINFO_SMART_CONCURRENT, 300 /* HOOK BEFORE REG INIT----------- */ 301 302 /* Dynamic value: */ 303 /* POINTER REFERENCE----------- */ 304 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 305 ODM_CMNINFO_TX_UNI, 306 ODM_CMNINFO_RX_UNI, 307 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 308 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 309 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 310 ODM_CMNINFO_BW, /* ODM_BW_E */ 311 ODM_CMNINFO_CHNL, 312 ODM_CMNINFO_FORCED_RATE, 313 314 ODM_CMNINFO_DMSP_GET_VALUE, 315 ODM_CMNINFO_BUDDY_ADAPTOR, 316 ODM_CMNINFO_DMSP_IS_MASTER, 317 ODM_CMNINFO_SCAN, 318 ODM_CMNINFO_POWER_SAVING, 319 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 320 ODM_CMNINFO_DRV_STOP, 321 ODM_CMNINFO_PNP_IN, 322 ODM_CMNINFO_INIT_ON, 323 ODM_CMNINFO_ANT_TEST, 324 ODM_CMNINFO_NET_CLOSED, 325 ODM_CMNINFO_MP_MODE, 326 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 327 ODM_CMNINFO_FORCED_IGI_LB, 328 ODM_CMNINFO_IS1ANTENNA, 329 ODM_CMNINFO_RFDEFAULTPATH, 330 /* POINTER REFERENCE----------- */ 331 332 /* CALL BY VALUE------------- */ 333 ODM_CMNINFO_WIFI_DIRECT, 334 ODM_CMNINFO_WIFI_DISPLAY, 335 ODM_CMNINFO_LINK_IN_PROGRESS, 336 ODM_CMNINFO_LINK, 337 ODM_CMNINFO_STATION_STATE, 338 ODM_CMNINFO_RSSI_MIN, 339 ODM_CMNINFO_DBG_COMP, /* u64 */ 340 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 341 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 342 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 343 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 344 ODM_CMNINFO_BT_ENABLED, 345 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 346 ODM_CMNINFO_BT_HS_RSSI, 347 ODM_CMNINFO_BT_OPERATION, 348 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 349 ODM_CMNINFO_BT_DISABLE_EDCA, 350 /* CALL BY VALUE------------- */ 351 352 /* Dynamic ptr array hook itms. */ 353 ODM_CMNINFO_STA_STATUS, 354 ODM_CMNINFO_PHY_STATUS, 355 ODM_CMNINFO_MAC_STATUS, 356 357 ODM_CMNINFO_MAX, 358 }; 359 360 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 361 enum { /* _ODM_Support_Ability_Definition */ 362 /* */ 363 /* BB ODM section BIT 0-15 */ 364 /* */ 365 ODM_BB_DIG = BIT0, 366 ODM_BB_RA_MASK = BIT1, 367 ODM_BB_DYNAMIC_TXPWR = BIT2, 368 ODM_BB_FA_CNT = BIT3, 369 ODM_BB_RSSI_MONITOR = BIT4, 370 ODM_BB_CCK_PD = BIT5, 371 ODM_BB_ANT_DIV = BIT6, 372 ODM_BB_PWR_SAVE = BIT7, 373 ODM_BB_PWR_TRAIN = BIT8, 374 ODM_BB_RATE_ADAPTIVE = BIT9, 375 ODM_BB_PATH_DIV = BIT10, 376 ODM_BB_PSD = BIT11, 377 ODM_BB_RXHP = BIT12, 378 ODM_BB_ADAPTIVITY = BIT13, 379 ODM_BB_CFO_TRACKING = BIT14, 380 381 /* MAC DM section BIT 16-23 */ 382 ODM_MAC_EDCA_TURBO = BIT16, 383 ODM_MAC_EARLY_MODE = BIT17, 384 385 /* RF ODM section BIT 24-31 */ 386 ODM_RF_TX_PWR_TRACK = BIT24, 387 ODM_RF_RX_GAIN_TRACK = BIT25, 388 ODM_RF_CALIBRATION = BIT26, 389 }; 390 391 /* ODM_CMNINFO_INTERFACE */ 392 enum { /* tag_ODM_Support_Interface_Definition */ 393 ODM_ITRF_SDIO = 0x4, 394 ODM_ITRF_ALL = 0x7, 395 }; 396 397 /* ODM_CMNINFO_IC_TYPE */ 398 enum { /* tag_ODM_Support_IC_Type_Definition */ 399 ODM_RTL8723B = BIT8, 400 }; 401 402 /* ODM_CMNINFO_CUT_VER */ 403 enum { /* tag_ODM_Cut_Version_Definition */ 404 ODM_CUT_A = 0, 405 ODM_CUT_B = 1, 406 ODM_CUT_C = 2, 407 ODM_CUT_D = 3, 408 ODM_CUT_E = 4, 409 ODM_CUT_F = 5, 410 411 ODM_CUT_I = 8, 412 ODM_CUT_J = 9, 413 ODM_CUT_K = 10, 414 ODM_CUT_TEST = 15, 415 }; 416 417 /* ODM_CMNINFO_FAB_VER */ 418 enum { /* tag_ODM_Fab_Version_Definition */ 419 ODM_TSMC = 0, 420 ODM_UMC = 1, 421 }; 422 423 /* */ 424 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 425 /* */ 426 enum { /* tag_ODM_RF_Type_Definition */ 427 ODM_1T1R = 0, 428 ODM_1T2R = 1, 429 ODM_2T2R = 2, 430 ODM_2T3R = 3, 431 ODM_2T4R = 4, 432 ODM_3T3R = 5, 433 ODM_3T4R = 6, 434 ODM_4T4R = 7, 435 }; 436 437 /* */ 438 /* ODM Dynamic common info value definition */ 439 /* */ 440 441 /* ODM_CMNINFO_WM_MODE */ 442 enum { /* tag_Wireless_Mode_Definition */ 443 ODM_WM_UNKNOWN = 0x0, 444 ODM_WM_B = BIT0, 445 ODM_WM_G = BIT1, 446 ODM_WM_N24G = BIT3, 447 ODM_WM_AUTO = BIT5, 448 }; 449 450 /* ODM_CMNINFO_BW */ 451 enum { /* tag_Bandwidth_Definition */ 452 ODM_BW20M = 0, 453 ODM_BW40M = 1, 454 }; 455 456 /* For AC-series IC, external PA & LNA can be individually added on 2.4G */ 457 458 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */ 459 TYPE_GPA0 = 0, 460 TYPE_GPA1 = BIT(1)|BIT(0) 461 }; 462 463 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */ 464 TYPE_APA0 = 0, 465 TYPE_APA1 = BIT(1)|BIT(0) 466 }; 467 468 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */ 469 TYPE_GLNA0 = 0, 470 TYPE_GLNA1 = BIT(2)|BIT(0), 471 TYPE_GLNA2 = BIT(3)|BIT(1), 472 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 473 }; 474 475 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */ 476 TYPE_ALNA0 = 0, 477 TYPE_ALNA1 = BIT(2)|BIT(0), 478 TYPE_ALNA2 = BIT(3)|BIT(1), 479 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 480 }; 481 482 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */ 483 bool bIQKDone; 484 s32 Value[3][IQK_Matrix_REG_NUM]; 485 bool bBWIqkResultSaved[3]; 486 }; 487 488 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 489 490 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */ 491 /* for tx power tracking */ 492 493 u32 RegA24; /* for TempCCK */ 494 s32 RegE94; 495 s32 RegE9C; 496 s32 RegEB4; 497 s32 RegEBC; 498 499 u8 TXPowercount; 500 bool bTXPowerTrackingInit; 501 bool bTXPowerTracking; 502 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 503 u8 TM_Trigger; 504 505 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 506 u8 ThermalValue; 507 u8 ThermalValue_LCK; 508 u8 ThermalValue_IQK; 509 u8 ThermalValue_DPK; 510 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 511 u8 ThermalValue_AVG_index; 512 u8 ThermalValue_RxGain; 513 u8 ThermalValue_Crystal; 514 u8 ThermalValue_DPKstore; 515 u8 ThermalValue_DPKtrack; 516 bool TxPowerTrackingInProgress; 517 518 bool bReloadtxpowerindex; 519 u8 bRfPiEnable; 520 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 521 522 /* Tx power Tracking ------------------------- */ 523 u8 bCCKinCH14; 524 u8 CCK_index; 525 u8 OFDM_index[MAX_RF_PATH]; 526 s8 PowerIndexOffset[MAX_RF_PATH]; 527 s8 DeltaPowerIndex[MAX_RF_PATH]; 528 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 529 bool bTxPowerChanged; 530 531 u8 ThermalValue_HP[HP_THERMAL_NUM]; 532 u8 ThermalValue_HP_index; 533 struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 534 bool bNeedIQK; 535 bool bIQKInProgress; 536 u8 Delta_IQK; 537 u8 Delta_LCK; 538 s8 BBSwingDiff2G; /* Unit: dB */ 539 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 540 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 541 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 542 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 543 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 544 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 545 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 546 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 547 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 548 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 549 550 /* */ 551 552 /* for IQK */ 553 u32 RegC04; 554 u32 Reg874; 555 u32 RegC08; 556 u32 RegB68; 557 u32 RegB6C; 558 u32 Reg870; 559 u32 Reg860; 560 u32 Reg864; 561 562 bool bIQKInitialized; 563 bool bLCKInProgress; 564 bool bAntennaDetected; 565 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 566 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 567 u32 IQK_BB_backup_recover[9]; 568 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 569 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 570 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 571 572 /* for APK */ 573 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 574 u8 bAPKdone; 575 u8 bAPKThermalMeterIgnore; 576 577 /* DPK */ 578 bool bDPKFail; 579 u8 bDPdone; 580 u8 bDPPathAOK; 581 u8 bDPPathBOK; 582 583 u32 TxLOK[2]; 584 585 }; 586 /* */ 587 /* ODM Dynamic common info value definition */ 588 /* */ 589 590 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */ 591 u8 Bssid[6]; 592 u8 antsel_rx_keep_0; 593 u8 antsel_rx_keep_1; 594 u8 antsel_rx_keep_2; 595 u8 antsel_rx_keep_3; 596 u32 antSumRSSI[7]; 597 u32 antRSSIcnt[7]; 598 u32 antAveRSSI[7]; 599 u8 FAT_State; 600 u32 TrainIdx; 601 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 602 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 603 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 604 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 605 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 606 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 607 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 608 u8 RxIdleAnt; 609 bool bBecomeLinked; 610 u32 MinMaxRSSI; 611 u8 idx_AntDiv_counter_2G; 612 u32 CCK_counter_main; 613 u32 CCK_counter_aux; 614 u32 OFDM_counter_main; 615 u32 OFDM_counter_aux; 616 617 u32 CCK_CtrlFrame_Cnt_main; 618 u32 CCK_CtrlFrame_Cnt_aux; 619 u32 OFDM_CtrlFrame_Cnt_main; 620 u32 OFDM_CtrlFrame_Cnt_aux; 621 u32 MainAnt_CtrlFrame_Sum; 622 u32 AuxAnt_CtrlFrame_Sum; 623 u32 MainAnt_CtrlFrame_Cnt; 624 u32 AuxAnt_CtrlFrame_Cnt; 625 626 }; 627 628 enum { 629 NO_ANTDIV = 0xFF, 630 CG_TRX_HW_ANTDIV = 0x01, 631 CGCS_RX_HW_ANTDIV = 0x02, 632 FIXED_HW_ANTDIV = 0x03, 633 CG_TRX_SMART_ANTDIV = 0x04, 634 CGCS_RX_SW_ANTDIV = 0x05, 635 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 636 }; 637 638 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */ 639 u8 RespTxPath; 640 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 641 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 642 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 643 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 644 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 645 }; 646 647 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */ 648 PHY_REG_PG_RELATIVE_VALUE = 0, 649 PHY_REG_PG_EXACT_VALUE = 1 650 }; 651 652 /* */ 653 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 654 /* */ 655 struct ant_detected_info { 656 bool bAntDetected; 657 u32 dBForAntA; 658 u32 dBForAntB; 659 u32 dBForAntO; 660 }; 661 662 /* */ 663 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 664 /* */ 665 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */ 666 /* struct timer_list FastAntTrainingTimer; */ 667 /* */ 668 /* Add for different team use temporarily */ 669 /* */ 670 struct adapter *Adapter; /* For CE/NIC team */ 671 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 672 bool odm_ready; 673 674 enum phy_reg_pg_type PhyRegPgValueType; 675 u8 PhyRegPgVersion; 676 677 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 678 u32 LastNumQryPhyStatusAll; 679 u32 RxPWDBAve; 680 bool MPDIG_2G; /* off MPDIG */ 681 u8 Times_2G; 682 683 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 684 bool bCckHighPower; 685 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 686 u8 ControlChannel; 687 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 688 689 /* REMOVED COMMON INFO---------- */ 690 /* u8 PseudoMacPhyMode; */ 691 /* bool *BTCoexist; */ 692 /* bool PseudoBtCoexist; */ 693 /* u8 OPMode; */ 694 /* bool bAPMode; */ 695 /* bool bClientMode; */ 696 /* bool bAdHocMode; */ 697 /* bool bSlaveOfDMSP; */ 698 /* REMOVED COMMON INFO---------- */ 699 700 /* 1 COMMON INFORMATION */ 701 702 /* */ 703 /* Init Value */ 704 /* */ 705 /* HOOK BEFORE REG INIT----------- */ 706 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 707 u8 SupportPlatform; 708 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 709 u32 SupportAbility; 710 /* ODM PCIE/USB/SDIO = 1/2/3 */ 711 u8 SupportInterface; 712 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 713 u32 SupportICType; 714 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 715 u8 CutVersion; 716 /* Fab Version TSMC/UMC = 0/1 */ 717 u8 FabVersion; 718 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 719 u8 RFEType; 720 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 721 u8 BoardType; 722 u8 PackageType; 723 u8 TypeGLNA; 724 u8 TypeGPA; 725 u8 TypeALNA; 726 u8 TypeAPA; 727 /* with external LNA NO/Yes = 0/1 */ 728 u8 ExtLNA; 729 /* with external PA NO/Yes = 0/1 */ 730 u8 ExtPA; 731 /* with external TRSW NO/Yes = 0/1 */ 732 u8 ExtTRSW; 733 u8 PatchID; /* Customer ID */ 734 bool bInHctTest; 735 bool bWIFITest; 736 737 bool bDualMacSmartConcurrent; 738 u32 BK_SupportAbility; 739 u8 AntDivType; 740 /* HOOK BEFORE REG INIT----------- */ 741 742 /* */ 743 /* Dynamic Value */ 744 /* */ 745 /* POINTER REFERENCE----------- */ 746 747 u8 u8_temp; 748 bool bool_temp; 749 struct adapter *adapter_temp; 750 751 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 752 u8 *pMacPhyMode; 753 /* TX Unicast byte count */ 754 u64 *pNumTxBytesUnicast; 755 /* RX Unicast byte count */ 756 u64 *pNumRxBytesUnicast; 757 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 758 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 759 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 760 u8 *pSecChOffset; 761 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 762 u8 *pSecurity; 763 /* BW info 20M/40M/80M = 0/1/2 */ 764 u8 *pBandWidth; 765 /* Central channel location Ch1/Ch2/.... */ 766 u8 *pChannel; /* central channel number */ 767 bool DPK_Done; 768 /* Common info for 92D DMSP */ 769 770 bool *pbGetValueFromOtherMac; 771 struct adapter **pBuddyAdapter; 772 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 773 /* Common info for Status */ 774 bool *pbScanInProcess; 775 bool *pbPowerSaving; 776 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 777 u8 *pOnePathCCA; 778 /* pMgntInfo->AntennaTest */ 779 u8 *pAntennaTest; 780 bool *pbNet_closed; 781 u8 *mp_mode; 782 /* u8 *pAidMap; */ 783 u8 *pu1ForcedIgiLb; 784 /* For 8723B IQK----------- */ 785 bool *pIs1Antenna; 786 u8 *pRFDefaultPath; 787 /* 0:S1, 1:S0 */ 788 789 /* POINTER REFERENCE----------- */ 790 u16 *pForcedDataRate; 791 /* CALL BY VALUE------------- */ 792 bool bLinkInProcess; 793 bool bWIFI_Direct; 794 bool bWIFI_Display; 795 bool bLinked; 796 797 bool bsta_state; 798 u8 RSSI_Min; 799 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 800 bool bOneEntryOnly; 801 /* Common info for BTDM */ 802 bool bBtEnabled; /* BT is disabled */ 803 bool bBtConnectProcess; /* BT HS is under connection progress. */ 804 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 805 bool bBtHsOperation; /* BT HS mode is under progress */ 806 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 807 bool bBtLimitedDig; /* BT is busy. */ 808 /* CALL BY VALUE------------- */ 809 u8 RSSI_A; 810 u8 RSSI_B; 811 u64 RSSI_TRSW; 812 u64 RSSI_TRSW_H; 813 u64 RSSI_TRSW_L; 814 u64 RSSI_TRSW_iso; 815 816 u8 RxRate; 817 bool bNoisyState; 818 u8 TxRate; 819 u8 LinkedInterval; 820 u8 preChannel; 821 u32 TxagcOffsetValueA; 822 bool IsTxagcOffsetPositiveA; 823 u32 TxagcOffsetValueB; 824 bool IsTxagcOffsetPositiveB; 825 u64 lastTxOkCnt; 826 u64 lastRxOkCnt; 827 u32 BbSwingOffsetA; 828 bool IsBbSwingOffsetPositiveA; 829 u32 BbSwingOffsetB; 830 bool IsBbSwingOffsetPositiveB; 831 s8 TH_L2H_ini; 832 s8 TH_EDCCA_HL_diff; 833 s8 IGI_Base; 834 u8 IGI_target; 835 bool ForceEDCCA; 836 u8 AdapEn_RSSI; 837 s8 Force_TH_H; 838 s8 Force_TH_L; 839 u8 IGI_LowerBound; 840 u8 antdiv_rssi; 841 u8 AntType; 842 u8 pre_AntType; 843 u8 antdiv_period; 844 u8 antdiv_select; 845 u8 NdpaPeriod; 846 bool H2C_RARpt_connect; 847 848 /* add by Yu Cehn for adaptivtiy */ 849 bool adaptivity_flag; 850 bool NHM_disable; 851 bool TxHangFlg; 852 bool Carrier_Sense_enable; 853 u8 tolerance_cnt; 854 u64 NHMCurTxOkcnt; 855 u64 NHMCurRxOkcnt; 856 u64 NHMLastTxOkcnt; 857 u64 NHMLastRxOkcnt; 858 u8 txEdcca1; 859 u8 txEdcca0; 860 s8 H2L_lb; 861 s8 L2H_lb; 862 u8 Adaptivity_IGI_upper; 863 u8 NHM_cnt_0; 864 865 /* */ 866 /* 2 Define STA info. */ 867 /* _ODM_STA_INFO */ 868 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 869 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 870 871 /* */ 872 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 873 /* We need to colelct all support abilit to a proper area. */ 874 /* */ 875 bool RaSupport88E; 876 877 /* Define ........... */ 878 879 /* Latest packet phy info (ODM write) */ 880 struct odm_phy_dbg_info PhyDbgInfo; 881 /* PHY_INFO_88E PhyInfo; */ 882 883 /* Latest packet phy info (ODM write) */ 884 struct odm_mac_status_info *pMacInfo; 885 /* MAC_INFO_88E MacInfo; */ 886 887 /* Different Team independt structure?? */ 888 889 /* */ 890 /* TX_RTP_CMN TX_retrpo; */ 891 /* TX_RTP_88E TX_retrpo; */ 892 /* TX_RTP_8195 TX_retrpo; */ 893 894 /* */ 895 /* ODM Structure */ 896 /* */ 897 struct fat_t DM_FatTable; 898 struct dig_t DM_DigTable; 899 struct ps_t DM_PSTable; 900 struct dynamic_primary_CCA DM_PriCCA; 901 struct rxhp_t dM_RXHP_Table; 902 struct ra_t DM_RA_Table; 903 struct false_ALARM_STATISTICS FalseAlmCnt; 904 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 905 struct swat_t DM_SWAT_Table; 906 bool RSSI_test; 907 struct cfo_tracking DM_CfoTrack; 908 909 struct edca_t DM_EDCA_Table; 910 u32 WMMEDCA_BE; 911 struct pathdiv_t DM_PathDiv; 912 /* Copy from SD4 structure */ 913 /* */ 914 /* ================================================== */ 915 /* */ 916 917 /* common */ 918 /* u8 DM_Type; */ 919 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 920 /* u8 PSD_func_flag; Add By Gary */ 921 /* for DIG */ 922 /* u8 bDMInitialGainEnable; */ 923 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 924 /* for Antenna diversity */ 925 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 926 /* PSTA_INFO_T RSSI_target; */ 927 928 bool *pbDriverStopped; 929 bool *pbDriverIsGoingToPnpSetPowerSleep; 930 bool *pinit_adpt_in_progress; 931 932 /* PSD */ 933 bool bUserAssignLevel; 934 struct timer_list PSDTimer; 935 u8 RSSI_BT; /* come from BT */ 936 bool bPSDinProcess; 937 bool bPSDactive; 938 bool bDMInitialGainEnable; 939 940 /* MPT DIG */ 941 struct timer_list MPT_DIGTimer; 942 943 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 944 u8 bUseRAMask; 945 946 struct odm_rate_adaptive RateAdaptive; 947 948 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */ 949 950 struct odm_rf_cal_t RFCalibrateInfo; 951 952 /* */ 953 /* TX power tracking */ 954 /* */ 955 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 956 u8 BbSwingIdxOfdmCurrent; 957 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 958 bool BbSwingFlagOfdm; 959 u8 BbSwingIdxCck; 960 u8 BbSwingIdxCckCurrent; 961 u8 BbSwingIdxCckBase; 962 u8 DefaultOfdmIndex; 963 u8 DefaultCckIndex; 964 bool BbSwingFlagCck; 965 966 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 967 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 968 s8 Remnant_CCKSwingIdx; 969 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 970 bool Modify_TxAGC_Flag_PathA; 971 bool Modify_TxAGC_Flag_PathB; 972 bool Modify_TxAGC_Flag_PathC; 973 bool Modify_TxAGC_Flag_PathD; 974 bool Modify_TxAGC_Flag_PathA_CCK; 975 976 s8 KfreeOffset[MAX_RF_PATH]; 977 /* */ 978 /* ODM system resource. */ 979 /* */ 980 981 /* ODM relative time. */ 982 struct timer_list PathDivSwitchTimer; 983 /* 2011.09.27 add for Path Diversity */ 984 struct timer_list CCKPathDiversityTimer; 985 struct timer_list FastAntTrainingTimer; 986 987 /* ODM relative workitem. */ 988 989 #if (BEAMFORMING_SUPPORT == 1) 990 RT_BEAMFORMING_INFO BeamformingInfo; 991 #endif 992 }; 993 994 enum odm_rf_content { 995 odm_radioa_txt = 0x1000, 996 odm_radiob_txt = 0x1001, 997 odm_radioc_txt = 0x1002, 998 odm_radiod_txt = 0x1003 999 }; 1000 1001 enum ODM_BB_Config_Type { 1002 CONFIG_BB_PHY_REG, 1003 CONFIG_BB_AGC_TAB, 1004 CONFIG_BB_AGC_TAB_2G, 1005 CONFIG_BB_PHY_REG_PG, 1006 CONFIG_BB_PHY_REG_MP, 1007 CONFIG_BB_AGC_TAB_DIFF, 1008 }; 1009 1010 enum ODM_RF_Config_Type { 1011 CONFIG_RF_RADIO, 1012 CONFIG_RF_TXPWR_LMT, 1013 }; 1014 1015 enum ODM_FW_Config_Type { 1016 CONFIG_FW_NIC, 1017 CONFIG_FW_NIC_2, 1018 CONFIG_FW_AP, 1019 CONFIG_FW_WoWLAN, 1020 CONFIG_FW_WoWLAN_2, 1021 CONFIG_FW_AP_WoWLAN, 1022 CONFIG_FW_BT, 1023 }; 1024 1025 #ifdef REMOVE_PACK 1026 #pragma pack() 1027 #endif 1028 1029 /* include "odm_function.h" */ 1030 1031 /* 3 =========================================================== */ 1032 /* 3 DIG */ 1033 /* 3 =========================================================== */ 1034 1035 /* Remove DIG by Yuchen */ 1036 1037 /* 3 =========================================================== */ 1038 /* 3 AGC RX High Power Mode */ 1039 /* 3 =========================================================== */ 1040 #define LNA_Low_Gain_1 0x64 1041 #define LNA_Low_Gain_2 0x5A 1042 #define LNA_Low_Gain_3 0x58 1043 1044 #define FA_RXHP_TH1 5000 1045 #define FA_RXHP_TH2 1500 1046 #define FA_RXHP_TH3 800 1047 #define FA_RXHP_TH4 600 1048 #define FA_RXHP_TH5 500 1049 1050 /* 3 =========================================================== */ 1051 /* 3 EDCA */ 1052 /* 3 =========================================================== */ 1053 1054 /* 3 =========================================================== */ 1055 /* 3 Dynamic Tx Power */ 1056 /* 3 =========================================================== */ 1057 /* Dynamic Tx Power Control Threshold */ 1058 1059 /* 3 =========================================================== */ 1060 /* 3 Rate Adaptive */ 1061 /* 3 =========================================================== */ 1062 #define DM_RATR_STA_INIT 0 1063 #define DM_RATR_STA_HIGH 1 1064 #define DM_RATR_STA_MIDDLE 2 1065 #define DM_RATR_STA_LOW 3 1066 1067 /* 3 =========================================================== */ 1068 /* 3 BB Power Save */ 1069 /* 3 =========================================================== */ 1070 1071 enum { /* tag_1R_CCA_Type_Definition */ 1072 CCA_1R = 0, 1073 CCA_2R = 1, 1074 CCA_MAX = 2, 1075 }; 1076 1077 enum { /* tag_RF_Type_Definition */ 1078 RF_Save = 0, 1079 RF_Normal = 1, 1080 RF_MAX = 2, 1081 }; 1082 1083 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1084 #define MAX_ANTENNA_DETECTION_CNT 10 1085 1086 /* */ 1087 /* Extern Global Variables. */ 1088 /* */ 1089 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1090 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1091 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1092 1093 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1094 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1095 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1096 1097 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1098 1099 /* */ 1100 /* check Sta pointer valid or not */ 1101 /* */ 1102 #define IS_STA_VALID(pSta) (pSta) 1103 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1104 /* This indicates two different the steps. */ 1105 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1106 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1107 /* with original RSSI to determine if it is necessary to switch antenna. */ 1108 #define SWAW_STEP_PEAK 0 1109 #define SWAW_STEP_DETERMINE 1 1110 1111 /* Remove BB power saving by Yuchen */ 1112 1113 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1114 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm); 1115 1116 bool ODM_RAStateCheck( 1117 struct dm_odm_t *pDM_Odm, 1118 s32 RSSI, 1119 bool bForceUpdate, 1120 u8 *pRATRState 1121 ); 1122 1123 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1124 void ODM_SwAntDivChkPerPktRssi( 1125 struct dm_odm_t *pDM_Odm, 1126 u8 StationID, 1127 struct odm_phy_info *pPhyInfo 1128 ); 1129 1130 u32 ODM_Get_Rate_Bitmap( 1131 struct dm_odm_t *pDM_Odm, 1132 u32 macid, 1133 u32 ra_mask, 1134 u8 rssi_level 1135 ); 1136 1137 #if (BEAMFORMING_SUPPORT == 1) 1138 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1139 #endif 1140 1141 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm); 1142 1143 void ODM_DMInit(struct dm_odm_t *pDM_Odm); 1144 1145 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1146 1147 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value); 1148 1149 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue); 1150 1151 void ODM_CmnInfoPtrArrayHook( 1152 struct dm_odm_t *pDM_Odm, 1153 enum odm_cmninfo_e CmnInfo, 1154 u16 Index, 1155 void *pValue 1156 ); 1157 1158 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1159 1160 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); 1161 1162 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); 1163 1164 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); 1165 1166 void ODM_AntselStatistics_88C( 1167 struct dm_odm_t *pDM_Odm, 1168 u8 MacId, 1169 u32 PWDBAll, 1170 bool isCCKrate 1171 ); 1172 1173 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State); 1174 1175 #endif 1176