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Searched refs:THM_TMON0_RDIL5_DATA__VALID_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_6_0_sh_mask.h388 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L macro
Dsmu_7_1_1_sh_mask.h3411 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 macro
Dsmu_7_1_0_sh_mask.h4193 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 macro
Dsmu_7_0_1_sh_mask.h4205 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 macro
Dsmu_7_1_2_sh_mask.h4327 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 macro
Dsmu_7_1_3_sh_mask.h4025 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 macro
/drivers/gpu/drm/amd/include/asic_reg/thm/
Dthm_10_0_sh_mask.h204 #define THM_TMON0_RDIL5_DATA__VALID_MASK … macro
Dthm_13_0_2_sh_mask.h356 #define THM_TMON0_RDIL5_DATA__VALID_MASK … macro
Dthm_9_0_sh_mask.h348 #define THM_TMON0_RDIL5_DATA__VALID_MASK … macro