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Searched refs:TST_CFG_WRITE_ON (Results 1 – 6 of 6) sorted by relevance

/drivers/net/fddi/skfp/
Ddrvfbi.c109 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_ON) ; /* enable for writes */ in card_start()
/drivers/net/fddi/skfp/h/
Dskfbi.h293 #define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */ macro
/drivers/net/ethernet/marvell/
Dsky2.c699 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_phy_power_up()
764 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_phy_power_down()
2351 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_qlink_intr()
2857 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_hw_intr()
2872 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_hw_intr()
3260 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_reset()
3323 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_reset()
Dskge.h246 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ enumerator
Dsky2.h509 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ enumerator
Dskge.c3329 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_error_irq()
3535 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3628 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()