Home
last modified time | relevance | path

Searched refs:UMC (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dumc_v6_1.c103 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
106 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
111 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
114 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
181 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT); in umc_v6_1_query_correctable_error_count()
183 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT); in umc_v6_1_query_correctable_error_count()
185 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT); in umc_v6_1_query_correctable_error_count()
189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); in umc_v6_1_query_correctable_error_count()
191 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); in umc_v6_1_query_correctable_error_count()
193 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_1_query_correctable_error_count()
[all …]
Dumc_v6_7.c81 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0); in umc_v6_7_query_error_status_helper()
88 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0); in umc_v6_7_query_error_status_helper()
95 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0); in umc_v6_7_query_error_status_helper()
287 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel); in umc_v6_7_query_correctable_error_count()
289 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt); in umc_v6_7_query_correctable_error_count()
291 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_query_correctable_error_count()
329 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v6_7_query_correctable_error_count()
358 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_querry_uncorrectable_error_count()
381 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()
384 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()
[all …]
Dumc_v8_7.c187 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_clear_error_count_per_channel()
189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_clear_error_count_per_channel()
245 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_query_correctable_error_count()
247 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_query_correctable_error_count()
249 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_correctable_error_count()
288 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_querry_uncorrectable_error_count()
336 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_error_address()
338 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_7_query_error_address()
397 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_err_cnt_init_per_channel()
399 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_err_cnt_init_per_channel()
Dumc_v8_10.c75 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); in umc_v8_10_clear_error_count_per_channel()
109 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_correctable_error_count()
127 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_uncorrectable_error_count()
217 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_error_address()
240 mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_10_query_error_address()
302 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel); in umc_v8_10_err_cnt_init_per_channel()
304 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); in umc_v8_10_err_cnt_init_per_channel()
340 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccCtrl); in umc_v8_10_query_ras_poison_mode_per_channel()
/drivers/net/ethernet/emulex/benet/
Dbe_cmds.h2221 UMC = 0x02, enumerator
Dbe_main.c4323 return UMC; in be_convert_mc_type()
5767 case UMC: in mc_name()