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Searched refs:UPLL_FB_DIV (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Drv770.c85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
92 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
110 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
123 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
Drv770d.h62 # define UPLL_FB_DIV(x) ((x) << 0) macro
Dsid.h146 # define UPLL_FB_DIV(x) ((x) << 0) macro
Devergreend.h367 # define UPLL_FB_DIV(x) ((x) << 0) macro
Dr600d.h1561 # define UPLL_FB_DIV(x) ((x) << 4) macro
Dr600.c257 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
Devergreen.c1237 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
Dsi.c7043 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h147 # define UPLL_FB_DIV(x) ((x) << 0) macro
Dsi.c1824 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()