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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
4  * Copyright (C) 2018,2019 Lubomir Rintel <lkundrak@v3.sk>
5  */
6 
7 #include <linux/delay.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/phy/phy.h>
11 #include <linux/platform_device.h>
12 #include <linux/soc/mmp/cputype.h>
13 
14 #define USB2_PLL_REG0		0x4
15 #define USB2_PLL_REG1		0x8
16 #define USB2_TX_REG0		0x10
17 #define USB2_TX_REG1		0x14
18 #define USB2_TX_REG2		0x18
19 #define USB2_RX_REG0		0x20
20 #define USB2_RX_REG1		0x24
21 #define USB2_RX_REG2		0x28
22 #define USB2_ANA_REG0		0x30
23 #define USB2_ANA_REG1		0x34
24 #define USB2_ANA_REG2		0x38
25 #define USB2_DIG_REG0		0x3C
26 #define USB2_DIG_REG1		0x40
27 #define USB2_DIG_REG2		0x44
28 #define USB2_DIG_REG3		0x48
29 #define USB2_TEST_REG0		0x4C
30 #define USB2_TEST_REG1		0x50
31 #define USB2_TEST_REG2		0x54
32 #define USB2_CHARGER_REG0	0x58
33 #define USB2_OTG_REG0		0x5C
34 #define USB2_PHY_MON0		0x60
35 #define USB2_RESETVE_REG0	0x64
36 #define USB2_ICID_REG0		0x78
37 #define USB2_ICID_REG1		0x7C
38 
39 /* USB2_PLL_REG0 */
40 
41 /* This is for Ax stepping */
42 #define USB2_PLL_FBDIV_SHIFT_MMP3		0
43 #define USB2_PLL_FBDIV_MASK_MMP3		(0xFF << 0)
44 
45 #define USB2_PLL_REFDIV_SHIFT_MMP3		8
46 #define USB2_PLL_REFDIV_MASK_MMP3		(0xF << 8)
47 
48 #define USB2_PLL_VDD12_SHIFT_MMP3		12
49 #define USB2_PLL_VDD18_SHIFT_MMP3		14
50 
51 /* This is for B0 stepping */
52 #define USB2_PLL_FBDIV_SHIFT_MMP3_B0		0
53 #define USB2_PLL_REFDIV_SHIFT_MMP3_B0		9
54 #define USB2_PLL_VDD18_SHIFT_MMP3_B0		14
55 #define USB2_PLL_FBDIV_MASK_MMP3_B0		0x01FF
56 #define USB2_PLL_REFDIV_MASK_MMP3_B0		0x3E00
57 
58 #define USB2_PLL_CAL12_SHIFT_MMP3		0
59 #define USB2_PLL_CALI12_MASK_MMP3		(0x3 << 0)
60 
61 #define USB2_PLL_VCOCAL_START_SHIFT_MMP3	2
62 
63 #define USB2_PLL_KVCO_SHIFT_MMP3		4
64 #define USB2_PLL_KVCO_MASK_MMP3			(0x7<<4)
65 
66 #define USB2_PLL_ICP_SHIFT_MMP3			8
67 #define USB2_PLL_ICP_MASK_MMP3			(0x7<<8)
68 
69 #define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3		12
70 
71 #define USB2_PLL_PU_PLL_SHIFT_MMP3		13
72 #define USB2_PLL_PU_PLL_MASK			(0x1 << 13)
73 
74 #define USB2_PLL_READY_MASK_MMP3		(0x1 << 15)
75 
76 /* USB2_TX_REG0 */
77 #define USB2_TX_IMPCAL_VTH_SHIFT_MMP3		8
78 #define USB2_TX_IMPCAL_VTH_MASK_MMP3		(0x7 << 8)
79 
80 #define USB2_TX_RCAL_START_SHIFT_MMP3		13
81 
82 /* USB2_TX_REG1 */
83 #define USB2_TX_CK60_PHSEL_SHIFT_MMP3		0
84 #define USB2_TX_CK60_PHSEL_MASK_MMP3		(0xf << 0)
85 
86 #define USB2_TX_AMP_SHIFT_MMP3			4
87 #define USB2_TX_AMP_MASK_MMP3			(0x7 << 4)
88 
89 #define USB2_TX_VDD12_SHIFT_MMP3		8
90 #define USB2_TX_VDD12_MASK_MMP3			(0x3 << 8)
91 
92 /* USB2_TX_REG2 */
93 #define USB2_TX_DRV_SLEWRATE_SHIFT		10
94 
95 /* USB2_RX_REG0 */
96 #define USB2_RX_SQ_THRESH_SHIFT_MMP3		4
97 #define USB2_RX_SQ_THRESH_MASK_MMP3		(0xf << 4)
98 
99 #define USB2_RX_SQ_LENGTH_SHIFT_MMP3		10
100 #define USB2_RX_SQ_LENGTH_MASK_MMP3		(0x3 << 10)
101 
102 /* USB2_ANA_REG1*/
103 #define USB2_ANA_PU_ANA_SHIFT_MMP3		14
104 
105 /* USB2_OTG_REG0 */
106 #define USB2_OTG_PU_OTG_SHIFT_MMP3		3
107 
108 struct mmp3_usb_phy {
109 	struct phy *phy;
110 	void __iomem *base;
111 };
112 
u2o_get(void __iomem * base,unsigned int offset)113 static unsigned int u2o_get(void __iomem *base, unsigned int offset)
114 {
115 	return readl_relaxed(base + offset);
116 }
117 
u2o_set(void __iomem * base,unsigned int offset,unsigned int value)118 static void u2o_set(void __iomem *base, unsigned int offset,
119 		unsigned int value)
120 {
121 	u32 reg;
122 
123 	reg = readl_relaxed(base + offset);
124 	reg |= value;
125 	writel_relaxed(reg, base + offset);
126 	readl_relaxed(base + offset);
127 }
128 
u2o_clear(void __iomem * base,unsigned int offset,unsigned int value)129 static void u2o_clear(void __iomem *base, unsigned int offset,
130 		unsigned int value)
131 {
132 	u32 reg;
133 
134 	reg = readl_relaxed(base + offset);
135 	reg &= ~value;
136 	writel_relaxed(reg, base + offset);
137 	readl_relaxed(base + offset);
138 }
139 
mmp3_usb_phy_init(struct phy * phy)140 static int mmp3_usb_phy_init(struct phy *phy)
141 {
142 	struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
143 	void __iomem *base = mmp3_usb_phy->base;
144 
145 	if (cpu_is_mmp3_a0()) {
146 		u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3
147 			| USB2_PLL_REFDIV_MASK_MMP3));
148 		u2o_set(base, USB2_PLL_REG0,
149 			0xd << USB2_PLL_REFDIV_SHIFT_MMP3
150 			| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3);
151 	} else if (cpu_is_mmp3_b0()) {
152 		u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0
153 			| USB2_PLL_FBDIV_MASK_MMP3_B0);
154 		u2o_set(base, USB2_PLL_REG0,
155 			0xd << USB2_PLL_REFDIV_SHIFT_MMP3_B0
156 			| 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3_B0);
157 	} else {
158 		dev_err(&phy->dev, "unsupported silicon revision\n");
159 		return -ENODEV;
160 	}
161 
162 	u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK
163 		| USB2_PLL_ICP_MASK_MMP3
164 		| USB2_PLL_KVCO_MASK_MMP3
165 		| USB2_PLL_CALI12_MASK_MMP3);
166 	u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3
167 		| 1 << USB2_PLL_LOCK_BYPASS_SHIFT_MMP3
168 		| 3 << USB2_PLL_ICP_SHIFT_MMP3
169 		| 3 << USB2_PLL_KVCO_SHIFT_MMP3
170 		| 3 << USB2_PLL_CAL12_SHIFT_MMP3);
171 
172 	u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3);
173 	u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3);
174 
175 	u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3
176 		| USB2_TX_AMP_MASK_MMP3
177 		| USB2_TX_CK60_PHSEL_MASK_MMP3);
178 	u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3
179 		| 4 << USB2_TX_AMP_SHIFT_MMP3
180 		| 4 << USB2_TX_CK60_PHSEL_SHIFT_MMP3);
181 
182 	u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT);
183 	u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT);
184 
185 	u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3);
186 	u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3);
187 
188 	u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3);
189 
190 	u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3);
191 
192 	return 0;
193 }
194 
mmp3_usb_phy_calibrate(struct phy * phy)195 static int mmp3_usb_phy_calibrate(struct phy *phy)
196 {
197 	struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
198 	void __iomem *base = mmp3_usb_phy->base;
199 	int loops;
200 
201 	/*
202 	 * PLL VCO and TX Impedance Calibration Timing:
203 	 *
204 	 *                _____________________________________
205 	 * PU  __________|
206 	 *                        _____________________________
207 	 * VCOCAL START _________|
208 	 *                                 ___
209 	 * REG_RCAL_START ________________|   |________|_______
210 	 *               | 200us | 400us  | 40| 400us  | USB PHY READY
211 	 */
212 
213 	udelay(200);
214 	u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3);
215 	udelay(400);
216 	u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
217 	udelay(40);
218 	u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
219 	udelay(400);
220 
221 	loops = 0;
222 	while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) {
223 		mdelay(1);
224 		loops++;
225 		if (loops > 100) {
226 			dev_err(&phy->dev, "PLL_READY not set after 100mS.\n");
227 			return -ETIMEDOUT;
228 		}
229 	}
230 
231 	return 0;
232 }
233 
234 static const struct phy_ops mmp3_usb_phy_ops = {
235 	.init		= mmp3_usb_phy_init,
236 	.calibrate	= mmp3_usb_phy_calibrate,
237 	.owner		= THIS_MODULE,
238 };
239 
240 static const struct of_device_id mmp3_usb_phy_of_match[] = {
241 	{ .compatible = "marvell,mmp3-usb-phy", },
242 	{ },
243 };
244 MODULE_DEVICE_TABLE(of, mmp3_usb_phy_of_match);
245 
mmp3_usb_phy_probe(struct platform_device * pdev)246 static int mmp3_usb_phy_probe(struct platform_device *pdev)
247 {
248 	struct device *dev = &pdev->dev;
249 	struct mmp3_usb_phy *mmp3_usb_phy;
250 	struct phy_provider *provider;
251 
252 	mmp3_usb_phy = devm_kzalloc(dev, sizeof(*mmp3_usb_phy), GFP_KERNEL);
253 	if (!mmp3_usb_phy)
254 		return -ENOMEM;
255 
256 	mmp3_usb_phy->base = devm_platform_ioremap_resource(pdev, 0);
257 	if (IS_ERR(mmp3_usb_phy->base)) {
258 		dev_err(dev, "failed to remap PHY regs\n");
259 		return PTR_ERR(mmp3_usb_phy->base);
260 	}
261 
262 	mmp3_usb_phy->phy = devm_phy_create(dev, NULL, &mmp3_usb_phy_ops);
263 	if (IS_ERR(mmp3_usb_phy->phy)) {
264 		dev_err(dev, "failed to create PHY\n");
265 		return PTR_ERR(mmp3_usb_phy->phy);
266 	}
267 
268 	phy_set_drvdata(mmp3_usb_phy->phy, mmp3_usb_phy);
269 	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
270 	if (IS_ERR(provider)) {
271 		dev_err(dev, "failed to register PHY provider\n");
272 		return PTR_ERR(provider);
273 	}
274 
275 	return 0;
276 }
277 
278 static struct platform_driver mmp3_usb_phy_driver = {
279 	.probe		= mmp3_usb_phy_probe,
280 	.driver		= {
281 		.name	= "mmp3-usb-phy",
282 		.of_match_table = mmp3_usb_phy_of_match,
283 	},
284 };
285 module_platform_driver(mmp3_usb_phy_driver);
286 
287 MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
288 MODULE_DESCRIPTION("Marvell MMP3 USB PHY Driver");
289 MODULE_LICENSE("GPL v2");
290