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Searched refs:UTMIP_PLL_CFG1_ENABLE_DLY_COUNT (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/tegra/
Dclk-pll.c185 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) macro
1176 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); in clk_pllu_enable()
1177 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_enable()
1799 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); in clk_pllu_tegra114_enable()
1800 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_tegra114_enable()
Dclk-tegra210.c171 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) macro
2838 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); in tegra210_utmi_param_configure()
2840 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); in tegra210_utmi_param_configure()