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Searched refs:UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h419 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT … macro
Duvd_4_2_sh_mask.h224 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
Duvd_3_1_sh_mask.h224 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
Duvd_4_0_sh_mask.h33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 macro
Duvd_5_0_sh_mask.h246 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
Duvd_6_0_sh_mask.h248 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c648 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v4_0_disable_clock_gating()
761 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v4_0_disable_clock_gating_dpg_mode()
816 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v4_0_enable_clock_gating()
Dvcn_v2_0.c500 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_0_disable_clock_gating()
602 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
660 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_0_enable_clock_gating()
Dvcn_v1_0.c475 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_disable_clock_gating()
598 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_enable_clock_gating()
659 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
Duvd_v3_1.c216 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | in uvd_v3_1_set_dcm()
Duvd_v4_2.c640 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | in uvd_v4_2_set_dcm()
Dvcn_v2_5.c567 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_5_disable_clock_gating()
673 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
732 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c705 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v3_0_disable_clock_gating()
833 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
889 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v3_0_enable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h912 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT … macro
Dvcn_2_5_sh_mask.h1980 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT … macro
Dvcn_2_0_0_sh_mask.h1930 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3651 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2710 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT … macro
Dvcn_4_0_0_sh_mask.h88 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT … macro