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Searched refs:UVD_CGC_UDEC_STATUS__CM_SCLK_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h273 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 macro
Duvd_3_1_sh_mask.h273 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 macro
Duvd_4_0_sh_mask.h210 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L macro
Duvd_5_0_sh_mask.h297 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 macro
Duvd_6_0_sh_mask.h299 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2044 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK … macro
Dvcn_2_0_0_sh_mask.h1996 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK … macro
Dvcn_2_6_0_sh_mask.h3715 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK … macro
Dvcn_3_0_0_sh_mask.h2774 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK … macro
Dvcn_4_0_0_sh_mask.h3892 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK … macro