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Searched refs:UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h116 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK … macro
Duvd_4_2_sh_mask.h41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 macro
Duvd_3_1_sh_mask.h41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 macro
Duvd_4_0_sh_mask.h249 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L macro
Duvd_5_0_sh_mask.h41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 macro
Duvd_6_0_sh_mask.h41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h306 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK … macro
Dvcn_2_5_sh_mask.h2195 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK … macro
Dvcn_2_0_0_sh_mask.h3166 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK … macro
Dvcn_2_6_0_sh_mask.h3866 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK … macro
Dvcn_3_0_0_sh_mask.h2961 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK … macro
Dvcn_4_0_0_sh_mask.h3973 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK … macro