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Searched refs:UVD_GPCOM_VCPU_CMD__CMD__SHIFT (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h114 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT … macro
Duvd_4_2_sh_mask.h44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 macro
Duvd_3_1_sh_mask.h44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 macro
Duvd_4_0_sh_mask.h251 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x00000001 macro
Duvd_5_0_sh_mask.h44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 macro
Duvd_6_0_sh_mask.h44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h304 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT … macro
Dvcn_2_5_sh_mask.h2193 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT … macro
Dvcn_2_0_0_sh_mask.h3164 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3864 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2959 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT … macro
Dvcn_4_0_0_sh_mask.h3971 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT … macro