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Searched refs:UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h123 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT … macro
Duvd_4_2_sh_mask.h50 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 macro
Duvd_3_1_sh_mask.h50 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h257 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x00000000 macro
Duvd_5_0_sh_mask.h50 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h50 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h313 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT … macro
Dvcn_2_5_sh_mask.h2202 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT … macro
Dvcn_2_0_0_sh_mask.h3173 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3873 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2968 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT … macro
Dvcn_4_0_0_sh_mask.h2910 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT … macro