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Searched refs:UVD_MPC_SET_MUXA1__VARA_5__SHIFT (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h609 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT … macro
Duvd_4_2_sh_mask.h492 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 macro
Duvd_3_1_sh_mask.h488 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h507 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000 macro
Duvd_5_0_sh_mask.h524 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h526 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1116 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT … macro
Dvcn_2_5_sh_mask.h2857 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2622 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2849 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3930 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4180 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT … macro