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Searched refs:UVD_MPC_SET_MUXA1__VARA_6_MASK (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h613 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
Duvd_4_2_sh_mask.h493 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
Duvd_3_1_sh_mask.h489 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
Duvd_4_0_sh_mask.h508 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000fc0L macro
Duvd_5_0_sh_mask.h525 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
Duvd_6_0_sh_mask.h527 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1120 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
Dvcn_2_5_sh_mask.h2861 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
Dvcn_2_0_0_sh_mask.h2626 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
Dvcn_2_6_0_sh_mask.h2853 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
Dvcn_3_0_0_sh_mask.h3934 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
Dvcn_4_0_0_sh_mask.h4184 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro