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Searched refs:UVD_MPC_SET_MUXB0__VARB_3__SHIFT (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h619 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT … macro
Duvd_4_2_sh_mask.h504 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
Duvd_3_1_sh_mask.h500 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
Duvd_4_0_sh_mask.h519 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012 macro
Duvd_5_0_sh_mask.h536 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
Duvd_6_0_sh_mask.h538 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1126 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT … macro
Dvcn_2_5_sh_mask.h2867 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2632 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2859 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3940 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4190 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c926 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_start_dpg_mode()
1065 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_start()
Dvcn_v2_0.c850 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_0_start_dpg_mode()
985 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_0_start()
Dvcn_v1_0.c836 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v1_0_start_spg_mode()
1019 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c832 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start_dpg_mode()
986 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start()
Dvcn_v3_0.c998 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v3_0_start_dpg_mode()
1164 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v3_0_start()