Home
last modified time | relevance | path

Searched refs:UVD_MPC_SET_MUXB0__VARB_4__SHIFT (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h620 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
Duvd_4_2_sh_mask.h506 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
Duvd_3_1_sh_mask.h502 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
Duvd_4_0_sh_mask.h521 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018 macro
Duvd_5_0_sh_mask.h538 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
Duvd_6_0_sh_mask.h540 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1127 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
Dvcn_2_5_sh_mask.h2868 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2633 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2860 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3941 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4191 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c927 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1066 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v4_0_start()
Dvcn_v2_0.c851 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v2_0_start_dpg_mode()
986 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v2_0_start()
Dvcn_v1_0.c837 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v1_0_start_spg_mode()
1020 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c833 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
987 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v2_5_start()
Dvcn_v3_0.c999 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1165 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v3_0_start()