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Searched refs:UVD_MPC_SET_MUXB1__VARB_5_MASK (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h630 #define UVD_MPC_SET_MUXB1__VARB_5_MASK … macro
Duvd_4_2_sh_mask.h507 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f macro
Duvd_3_1_sh_mask.h503 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f macro
Duvd_4_0_sh_mask.h522 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003fL macro
Duvd_5_0_sh_mask.h539 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f macro
Duvd_6_0_sh_mask.h541 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1137 #define UVD_MPC_SET_MUXB1__VARB_5_MASK … macro
Dvcn_2_5_sh_mask.h2878 #define UVD_MPC_SET_MUXB1__VARB_5_MASK … macro
Dvcn_2_0_0_sh_mask.h2643 #define UVD_MPC_SET_MUXB1__VARB_5_MASK … macro
Dvcn_2_6_0_sh_mask.h2870 #define UVD_MPC_SET_MUXB1__VARB_5_MASK … macro
Dvcn_3_0_0_sh_mask.h3951 #define UVD_MPC_SET_MUXB1__VARB_5_MASK … macro
Dvcn_4_0_0_sh_mask.h4201 #define UVD_MPC_SET_MUXB1__VARB_5_MASK … macro