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Searched refs:UVD_MPC_SET_MUX__SET_2__SHIFT (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h636 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
Duvd_4_2_sh_mask.h518 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
Duvd_3_1_sh_mask.h514 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
Duvd_4_0_sh_mask.h533 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006 macro
Duvd_5_0_sh_mask.h550 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
Duvd_6_0_sh_mask.h552 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1143 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
Dvcn_2_5_sh_mask.h2884 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2649 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2876 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3957 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4207 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c933 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1072 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v4_0_start()
Dvcn_v2_0.c857 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v2_0_start_dpg_mode()
992 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v2_0_start()
Dvcn_v1_0.c842 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v1_0_start_spg_mode()
1025 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c839 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
993 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v2_5_start()
Dvcn_v3_0.c1005 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1171 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v3_0_start()