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Searched refs:UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c896 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, in vcn_v2_0_start_dpg_mode()
897 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_0_start_dpg_mode()
925 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_0_start_dpg_mode()
1231 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, in vcn_v2_0_pause_dpg_mode()
1232 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_0_pause_dpg_mode()
1260 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_0_pause_dpg_mode()
Dvcn_v2_5.c883 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, in vcn_v2_5_start_dpg_mode()
884 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_5_start_dpg_mode()
912 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_5_start_dpg_mode()
1434 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, in vcn_v2_5_pause_dpg_mode()
1435 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_5_pause_dpg_mode()
1460 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_5_pause_dpg_mode()
Dvcn_v3_0.c1053 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, in vcn_v3_0_start_dpg_mode()
1054 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v3_0_start_dpg_mode()
1088 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v3_0_start_dpg_mode()
1627 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, in vcn_v3_0_pause_dpg_mode()
1628 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v3_0_pause_dpg_mode()
1660 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v3_0_pause_dpg_mode()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h1526 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK … macro
Dvcn_2_0_0_sh_mask.h1523 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK … macro
Dvcn_2_6_0_sh_mask.h2964 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK … macro
Dvcn_3_0_0_sh_mask.h2060 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK … macro
Dvcn_4_0_0_sh_mask.h6353 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK … macro