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Searched refs:UVD_POWER_STATUS__UVD_PG_EN_MASK (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h42 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
Duvd_5_0_sh_mask.h939 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 macro
Duvd_6_0_sh_mask.h927 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h83 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
Dvcn_2_5_sh_mask.h1523 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
Dvcn_2_0_0_sh_mask.h1520 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
Dvcn_2_6_0_sh_mask.h2961 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
Dvcn_3_0_0_sh_mask.h2057 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
Dvcn_4_0_0_sh_mask.h6350 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c568 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_disable_static_power_gating()
880 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_start_dpg_mode()
Dvcn_v2_0.c745 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_0_disable_static_power_gating()
803 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_0_start_dpg_mode()
Dvcn_v1_0.c733 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_1_0_disable_static_power_gating()
974 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v1_0_start_dpg_mode()
Dvcn_v3_0.c637 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v3_0_disable_static_power_gating()
951 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v3_0_start_dpg_mode()
Duvd_v6_0.c1483 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); in uvd_v6_0_set_powergating_state()
Duvd_v7_0.c1762 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
Dvcn_v2_5.c785 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_5_start_dpg_mode()