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Searched refs:UVD_POWER_STATUS__UVD_PG_MODE_MASK (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h37 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
Duvd_5_0_sh_mask.h929 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
Duvd_6_0_sh_mask.h917 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
Dvcn_2_5_sh_mask.h1521 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
Dvcn_2_0_0_sh_mask.h1518 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
Dvcn_2_6_0_sh_mask.h2959 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
Dvcn_3_0_0_sh_mask.h2055 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
Dvcn_4_0_0_sh_mask.h6348 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c879 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v4_0_start_dpg_mode()
1400 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v4_0_stop_dpg_mode()
Dvcn_v2_0.c802 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v2_0_start_dpg_mode()
1127 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v2_0_stop_dpg_mode()
Dvcn_v1_0.c973 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v1_0_start_dpg_mode()
1191 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v1_0_stop_dpg_mode()
Dvcn_v2_5.c784 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v2_5_start_dpg_mode()
1329 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v2_5_stop_dpg_mode()
Dvcn_v3_0.c950 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v3_0_start_dpg_mode()
1516 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v3_0_stop_dpg_mode()
Duvd_v6_0.c729 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in uvd_v6_0_start()
Duvd_v7_0.c961 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in uvd_v7_0_start()