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Searched refs:UVD_RB_ARB_CTRL__VCPU_DIS_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c1082 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_start()
1450 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v4_0_stop()
1451 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_stop()
Dvcn_v2_5.c1014 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v2_5_start()
1373 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v2_5_stop()
1374 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v2_5_stop()
Dvcn_v3_0.c1181 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v3_0_start()
1560 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v3_0_stop()
1561 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v3_0_stop()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2543 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_2_0_0_sh_mask.h1769 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_2_6_0_sh_mask.h4371 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_3_0_0_sh_mask.h3483 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_4_0_0_sh_mask.h3378 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro