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Searched refs:UVD_RB_BASE_HI4__RB_BASE_HI_MASK (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1349 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK … macro
Dvcn_2_5_sh_mask.h2505 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK … macro
Dvcn_2_0_0_sh_mask.h3074 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK … macro
Dvcn_2_6_0_sh_mask.h4327 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK … macro
Dvcn_3_0_0_sh_mask.h3434 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK … macro
Dvcn_4_0_0_sh_mask.h3346 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK … macro