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Searched refs:UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h340 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT … macro
Duvd_4_2_sh_mask.h110 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 macro
Duvd_3_1_sh_mask.h110 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h629 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x00000000 macro
Duvd_5_0_sh_mask.h122 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h124 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h701 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT … macro
Dvcn_2_5_sh_mask.h2984 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT … macro
Dvcn_2_0_0_sh_mask.h1737 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3316 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT … macro
Dvcn_3_0_0_sh_mask.h4072 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4316 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT … macro