Home
last modified time | relevance | path

Searched refs:UVD_STATUS__VCPU_REPORT__SHIFT (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h752 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
Duvd_4_2_sh_mask.h632 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 macro
Duvd_3_1_sh_mask.h626 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 macro
Duvd_4_0_sh_mask.h693 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001 macro
Duvd_5_0_sh_mask.h694 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 macro
Duvd_6_0_sh_mask.h696 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1279 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
Dvcn_2_5_sh_mask.h1735 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2903 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3371 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2424 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
Dvcn_4_0_0_sh_mask.h3612 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v7_0.c909 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); in uvd_v7_0_sriov_start()
1076 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v7_0_start()
Duvd_v6_0.c829 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start()
Dvcn_v4_0.c1136 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in vcn_v4_0_start()
Dvcn_v2_0.c1053 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in vcn_v2_0_start()
Dvcn_v2_5.c1059 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in vcn_v2_5_start()
Dvcn_v3_0.c1224 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in vcn_v3_0_start()