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Searched refs:UVD_SUVD_CGC_CTRL__SDB_MODE_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h259 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK macro
Duvd_5_0_sh_mask.h793 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 macro
Duvd_6_0_sh_mask.h787 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c716 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); in uvd_v5_0_set_sw_clock_gating()
Dvcn_v4_0.c732 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v4_0_disable_clock_gating()
848 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v4_0_enable_clock_gating()
Dvcn_v2_0.c583 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v2_0_disable_clock_gating()
692 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v2_0_enable_clock_gating()
Dvcn_v1_0.c558 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v1_0_disable_clock_gating()
630 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v1_0_enable_clock_gating()
Dvcn_v2_5.c653 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v2_5_disable_clock_gating()
763 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c805 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v3_0_disable_clock_gating()
921 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK in vcn_v3_0_enable_clock_gating()
Duvd_v6_0.c1374 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1656 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h551 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK macro
Dvcn_2_5_sh_mask.h2184 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK macro
Dvcn_2_0_0_sh_mask.h3310 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK macro
Dvcn_2_6_0_sh_mask.h3855 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK macro
Dvcn_3_0_0_sh_mask.h2941 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK macro
Dvcn_4_0_0_sh_mask.h2869 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK macro