Home
last modified time | relevance | path

Searched refs:UVD_SUVD_CGC_CTRL__SITE_MODE_MASK (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h556 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK … macro
Dvcn_2_5_sh_mask.h2189 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK … macro
Dvcn_2_0_0_sh_mask.h3315 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK … macro
Dvcn_2_6_0_sh_mask.h3860 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK … macro
Dvcn_3_0_0_sh_mask.h2946 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK … macro
Dvcn_4_0_0_sh_mask.h2874 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c737 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v4_0_disable_clock_gating()
853 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v4_0_enable_clock_gating()
Dvcn_v2_0.c588 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v2_0_disable_clock_gating()
697 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v2_0_enable_clock_gating()
Dvcn_v1_0.c563 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v1_0_disable_clock_gating()
635 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v1_0_enable_clock_gating()
Dvcn_v2_5.c658 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v2_5_disable_clock_gating()
768 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c809 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK in vcn_v3_0_disable_clock_gating()
925 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK in vcn_v3_0_enable_clock_gating()