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Searched refs:UVD_SUVD_CGC_GATE__SRE_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c661 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
694 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
1284 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | in uvd_v6_0_enable_clock_gating()
1409 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
Duvd_v5_0.c636 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | in uvd_v5_0_enable_clock_gating()
749 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
Duvd_v7_0.c1620 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1693 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
Dvcn_v4_0.c701 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v4_0_disable_clock_gating()
Dvcn_v2_0.c552 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v1_0.c527 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c622 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v3_0.c759 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h226 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
Duvd_5_0_sh_mask.h723 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 macro
Duvd_6_0_sh_mask.h725 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h454 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
Dvcn_2_5_sh_mask.h2083 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
Dvcn_2_0_0_sh_mask.h3209 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
Dvcn_2_6_0_sh_mask.h3754 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
Dvcn_3_0_0_sh_mask.h2819 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
Dvcn_4_0_0_sh_mask.h1336 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro