Home
last modified time | relevance | path

Searched refs:UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h535 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK … macro
Dvcn_2_5_sh_mask.h2166 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK … macro
Dvcn_2_0_0_sh_mask.h3292 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK … macro
Dvcn_2_6_0_sh_mask.h3837 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK … macro
Dvcn_3_0_0_sh_mask.h2911 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK … macro
Dvcn_4_0_0_sh_mask.h3964 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK … macro