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Searched refs:UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h761 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 macro
Duvd_6_0_sh_mask.h759 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h512 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK … macro
Dvcn_2_5_sh_mask.h2143 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK … macro
Dvcn_2_0_0_sh_mask.h3269 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK … macro
Dvcn_2_6_0_sh_mask.h3814 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK … macro
Dvcn_3_0_0_sh_mask.h2888 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK … macro
Dvcn_4_0_0_sh_mask.h3941 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK … macro