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Searched refs:UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h502 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT … macro
Dvcn_2_5_sh_mask.h2132 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT … macro
Dvcn_2_0_0_sh_mask.h3258 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3803 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2874 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT … macro
Dvcn_4_0_0_sh_mask.h3927 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT … macro