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Searched refs:UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h766 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 macro
Duvd_6_0_sh_mask.h764 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h486 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
Dvcn_2_5_sh_mask.h2116 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
Dvcn_2_0_0_sh_mask.h3242 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3787 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2858 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
Dvcn_4_0_0_sh_mask.h3911 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro