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Searched refs:UVD_VCPU_CNTL__CLK_EN_MASK (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c891 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_start_dpg_mode()
938 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v4_0_start_dpg_mode()
1025 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v4_0_start()
1460 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v4_0_stop()
Dvcn_v2_5.c796 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()
857 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()
954 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_5_start()
1383 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_5_stop()
Dvcn_v3_0.c962 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()
1023 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()
1124 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v3_0_start()
1570 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v3_0_stop()
Dvcn_v2_0.c814 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_0_start_dpg_mode()
954 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_0_start()
1170 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_0_stop()
Dvcn_v1_0.c851 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_start_spg_mode()
982 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v1_0_start_dpg_mode()
1140 ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_stop_spg_mode()
Duvd_v7_0.c900 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_sriov_start()
1031 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_start()
Duvd_v6_0.c789 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v6_0_start()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h665 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
Duvd_4_2_sh_mask.h547 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
Duvd_3_1_sh_mask.h543 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
Duvd_4_0_sh_mask.h768 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
Duvd_5_0_sh_mask.h579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
Duvd_6_0_sh_mask.h581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1187 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
Dvcn_2_5_sh_mask.h2759 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
Dvcn_2_0_0_sh_mask.h2759 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
Dvcn_2_6_0_sh_mask.h112 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
Dvcn_3_0_0_sh_mask.h3818 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
Dvcn_4_0_0_sh_mask.h4066 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro