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Searched refs:UVD_VCPU_CNTL__TRCE_EN__SHIFT (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h550 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa macro
Duvd_3_1_sh_mask.h546 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa macro
Duvd_4_0_sh_mask.h789 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0x0000000a macro
Duvd_5_0_sh_mask.h582 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa macro
Duvd_6_0_sh_mask.h584 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2748 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2744 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT … macro
Dvcn_2_6_0_sh_mask.h101 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3806 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4052 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT … macro