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Searched refs:UvdBootLevel (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmumgr.h48 UvdBootLevel, enumerator
Dsmu7_fusion.h240 uint8_t UvdBootLevel; member
Dsmu7_discrete.h337 uint8_t UvdBootLevel; member
Dsmu74_discrete.h298 uint8_t UvdBootLevel; member
Dsmu72_discrete.h279 uint8_t UvdBootLevel; member
Dsmu73_discrete.h263 uint8_t UvdBootLevel; member
Dsmu75_discrete.h303 uint8_t UvdBootLevel; member
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c338 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()
340 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table()
343 UvdBootLevel); in vegam_update_uvd_smc_table()
349 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in vegam_update_uvd_smc_table()
359 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in vegam_update_uvd_smc_table()
1322 table->UvdBootLevel = 0; in vegam_populate_smc_uvd_level()
2187 case UvdBootLevel: in vegam_get_offsetof()
2188 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel); in vegam_get_offsetof()
Dfiji_smumgr.c1565 table->UvdBootLevel = 0; in fiji_populate_smc_uvd_level()
2326 case UvdBootLevel: in fiji_get_offsetof()
2327 return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel); in fiji_get_offsetof()
2372 smu_data->smc_state_table.UvdBootLevel = 0; in fiji_update_uvd_smc_table()
2374 smu_data->smc_state_table.UvdBootLevel = in fiji_update_uvd_smc_table()
2377 UvdBootLevel); in fiji_update_uvd_smc_table()
2383 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in fiji_update_uvd_smc_table()
2393 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in fiji_update_uvd_smc_table()
Dpolaris10_smumgr.c1534 table->UvdBootLevel = 0; in polaris10_populate_smc_uvd_level()
2288 smu_data->smc_state_table.UvdBootLevel = 0; in polaris10_update_uvd_smc_table()
2290 smu_data->smc_state_table.UvdBootLevel = in polaris10_update_uvd_smc_table()
2293 UvdBootLevel); in polaris10_update_uvd_smc_table()
2299 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in polaris10_update_uvd_smc_table()
2309 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in polaris10_update_uvd_smc_table()
2451 case UvdBootLevel: in polaris10_get_offsetof()
2452 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); in polaris10_get_offsetof()
Dtonga_smumgr.c1321 table->UvdBootLevel = 0; in tonga_populate_smc_uvd_level()
2637 case UvdBootLevel: in tonga_get_offsetof()
2638 return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); in tonga_get_offsetof()
2683 smu_data->smc_state_table.UvdBootLevel = 0; in tonga_update_uvd_smc_table()
2685 smu_data->smc_state_table.UvdBootLevel = in tonga_update_uvd_smc_table()
2688 offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); in tonga_update_uvd_smc_table()
2694 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in tonga_update_uvd_smc_table()
2705 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in tonga_update_uvd_smc_table()
Dci_smumgr.c2013 table->UvdBootLevel = 0; in ci_init_smc_table()
2872 smu_data->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_smc_table()
2874 smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1; in ci_update_uvd_smc_table()
2877 UvdBootLevel, smu_data->smc_state_table.UvdBootLevel); in ci_update_uvd_smc_table()
/drivers/gpu/drm/radeon/
Dsmu7_fusion.h240 uint8_t UvdBootLevel; member
Dsmu7_discrete.h336 uint8_t UvdBootLevel; member
Dci_dpm.c3583 table->UvdBootLevel = 0; in ci_init_smc_table()
4046 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4048 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4053 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
Dcikd.h51 # define UvdBootLevel(x) ((x) << 24) macro
Dkv_dpm.c1266 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), in kv_update_uvd_dpm()
/drivers/gpu/drm/amd/pm/legacy-dpm/
Dkv_dpm.c1532 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), in kv_update_uvd_dpm()