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Searched refs:VLINE_ACK (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_enums.h29 #define VLINE_ACK (1 << 4) macro
Dsid.h809 # define VLINE_ACK (1 << 4) macro
Ddce_v6_0.c2982 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); in dce_v6_0_crtc_irq()
Ddce_v10_0.c3233 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); in dce_v10_0_crtc_vline_int_ack()
Ddce_v11_0.c3356 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); in dce_v11_0_crtc_vline_int_ack()
/drivers/gpu/drm/radeon/
Dsid.h806 # define VLINE_ACK (1 << 4) macro
Dcik.c7323 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7327 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7339 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7343 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7356 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7360 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dcikd.h877 # define VLINE_ACK (1 << 4) macro
Devergreend.h1271 # define VLINE_ACK (1 << 4) macro
Devergreen.c4642 VLINE_ACK); in evergreen_irq_ack()
Dsi.c6173 VLINE_ACK); in si_irq_ack()