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/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dcore.h62 #define mlx5_fpga_dbg(__adev, format, ...) \ argument
63 mlx5_core_dbg((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
66 #define mlx5_fpga_err(__adev, format, ...) \ argument
67 mlx5_core_err((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
70 #define mlx5_fpga_warn(__adev, format, ...) \ argument
71 mlx5_core_warn((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
74 #define mlx5_fpga_warn_ratelimited(__adev, format, ...) \ argument
75 mlx5_core_err_rl((__adev)->mdev, "FPGA: %s:%d: " \
78 #define mlx5_fpga_notice(__adev, format, ...) \ argument
79 mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
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