Home
last modified time | relevance | path

Searched refs:_o (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/nouveau/include/nvif/
Dprintf.h8 struct nvif_object *_o = (o); \
9 struct nvif_parent *_p = _o->parent; \
10 _p->func->l(_o, "[%s/%08x:%s] "f"\n", _o->client->object.name, _o->handle, _o->name, ##a); \
/drivers/gpu/drm/armada/
Darmada_crtc.h18 #define armada_reg_queue_mod(_r, _i, _v, _m, _o) \ argument
21 __reg[_i].offset = _o; \
27 #define armada_reg_queue_set(_r, _i, _v, _o) \ argument
28 armada_reg_queue_mod(_r, _i, _v, ~0, _o)
/drivers/gpu/drm/nouveau/include/nvkm/core/
Dmemory.h104 u64 _a = (a), _c = (c), _d = (d), _o = _a >> s, _s = _c << s; \
109 iowrite##t##_native(_d, &_m[_o++]); \
111 memset_io(&_m[_o], _d, _s); \
/drivers/net/wireless/ath/ath5k/
Deeprom.h244 #define AR5K_EEPROM_READ(_o, _v) do { \ argument
245 if (!ath5k_hw_nvram_read(ah, (_o), &(_v))) \
249 #define AR5K_EEPROM_READ_HDR(_o, _v) \ argument
250 AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
/drivers/gpu/drm/msm/adreno/
Da5xx_power.c21 #define AGC_MSG_PAYLOAD(_o) ((AGC_MSG_BASE + 5) + (_o)) argument
/drivers/net/dsa/
Dmt7530.h686 #define MIB_DESC(_s, _o, _n) \ argument
689 .offset = (_o), \
/drivers/net/dsa/qca/
Dqca8k-common.c15 #define MIB_DESC(_s, _o, _n) \ argument
18 .offset = (_o), \