Home
last modified time | relevance | path

Searched refs:_offset (Results 1 – 25 of 81) sorted by relevance

1234

/drivers/thermal/qcom/
Dtsens.h81 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ argument
82 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
83 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
84 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
85 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
86 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
87 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
88 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
89 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
90 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
[all …]
/drivers/clk/bcm/
Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
93 .offset = (_offset), \
151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
153 .offset = (_offset), \
163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
165 .offset = (_offset), \
174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
176 .offset = (_offset), \
185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
187 .offset = (_offset), \
[all …]
/drivers/net/ethernet/mellanox/mlxsw/
Dcore_acl_flex_keys.h52 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
57 .offset = _offset, \
64 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
66 _element, _offset, _shift, _size)
68 #define MLXSW_AFK_ELEMENT_INFO_BUF(_element, _offset, _size) \ argument
70 _element, _offset, 0, _size)
84 #define MLXSW_AFK_ELEMENT_INST(_type, _element, _offset, \ argument
90 .offset = _offset, \
99 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
101 _element, _offset, _shift, _size, 0, false)
[all …]
Ditem.h266 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
268 .offset = _offset, \
284 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
287 .offset = _offset, \
309 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
311 .offset = _offset, \
327 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
330 .offset = _offset, \
352 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
354 .offset = _offset, \
[all …]
Dspectrum_acl.c519 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \ argument
522 .offset = _offset, \
528 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \ argument
530 _offset, _mask, _shift, _field)
532 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \ argument
534 _offset, _mask, _shift, _field)
536 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \ argument
537 MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_TCP, _offset, _mask, _shift, _field)
539 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \ argument
540 MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_UDP, _offset, _mask, _shift, _field)
/drivers/clk/tegra/
Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
146 #define MUX8(_name, _parents, _offset, \ argument
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
154 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
[all …]
Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
56 .offset = _offset,\
71 #define AUDIO2X(_name, _num, _offset) \ argument
79 .div_offset = _offset,\
/drivers/clk/renesas/
Drcar-gen4-cpg.h35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
49 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ argument
50 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
Drcar-gen3-cpg.h36 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
37 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
39 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
40 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
59 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
60 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
Drenesas-cpg-mssr.h53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
/drivers/bcma/
Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
186 bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
189 bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
190 sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
194 SPEX(_field[0], _offset + 0, _mask, _shift); \
195 SPEX(_field[1], _offset + 2, _mask, _shift); \
196 SPEX(_field[2], _offset + 4, _mask, _shift); \
197 SPEX(_field[3], _offset + 6, _mask, _shift); \
[all …]
/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
112 .offset = _offset, \
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
137 .offset = _offset, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
162 .offset = _offset, \
/drivers/clk/sunxi-ng/
Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
21 .offset = _offset, \
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
/drivers/video/fbdev/vermilion/
Dvermilion.h240 #define VML_READ32(_par, _offset) \ argument
241 (ioread32((_par)->vdc_mem + (_offset)))
242 #define VML_WRITE32(_par, _offset, _value) \ argument
243 iowrite32(_value, (_par)->vdc_mem + (_offset))
/drivers/staging/r8188eu/core/
Drtw_efuse.c25 u16 _offset, in ReadEFuseByte() argument
34 rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff)); in ReadEFuseByte()
39 rtw_write8(Adapter, EFUSE_CTRL + 2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); in ReadEFuseByte()
/drivers/ssb/
Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
172 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
174 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
175 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
177 SPEX16(_outvar, _offset, _mask, _shift)
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
181 SPEX(_field[0], _offset + 0, _mask, _shift); \
182 SPEX(_field[1], _offset + 2, _mask, _shift); \
[all …]
/drivers/pinctrl/berlin/
Dberlin.h37 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
40 .offset = _offset, \
/drivers/clk/st/
Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
39 .offset = _offset, \
/drivers/clk/microchip/
Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
105 .reg_offset = _offset, \
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
128 .reg_offset = _offset, \
Dclk-mpfs.c172 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
176 .reg_offset = _offset, \
211 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
216 .reg_offset = _offset, \
/drivers/clk/stm32/
Dclk-stm32mp13.c138 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
140 .offset = (_offset),\
145 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
146 _CFG_GATE(_id, _offset, _bit_idx, 0)
148 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
149 _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
288 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
290 .offset = (_offset),\
350 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\ argument
352 .offset = (_offset),\
[all …]
/drivers/clk/
Dclk-stm32mp1.c1166 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1173 .reg_off = _offset,\
1193 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1201 .reg_off = _offset,\
1210 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1211 DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1214 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1222 .reg_off = _offset,\
1307 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1309 _GATE_MP1(_offset, _bit_idx, _gate_flags))
[all …]
/drivers/net/wireless/realtek/rtlwifi/
Defuse.h74 void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
79 void read_efuse(struct ieee80211_hw *hw, u16 _offset,
/drivers/staging/rtl8723bs/core/
Drtw_efuse.c148 u16 _offset,
157 u16 _offset, in efuse_ReadEFuse() argument
163 Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); in efuse_ReadEFuse()
/drivers/clk/keystone/
Dsyscon-clk.c135 #define TI_SYSCON_CLK_GATE(_name, _offset, _bit_idx) \ argument
138 .offset = (_offset), \

1234