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Searched refs:_table (Results 1 – 22 of 22) sorted by relevance

/drivers/clk/sprd/
Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
36 .table = _table, \
39 #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \ argument
42 .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
51 #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \ argument
53 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
62 #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \ argument
64 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
25 .mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
/drivers/clk/actions/
Dowl-pll.h42 _width, _min_mul, _max_mul, _delay, _table) \ argument
52 .table = _table, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
60 OWL_PLL_DEF_DELAY, _table), \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
75 OWL_PLL_DEF_DELAY, _table), \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
90 _delay, _table), \
Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
35 .table = _table, \
39 _shift, _width, _table, _div_flags, _flags) \ argument
42 _div_flags, _table), \
Dowl-factor.h35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ argument
41 .table = _table, \
45 _shift, _width, _table, _fct_flags, _flags) \ argument
48 _width, _fct_flags, _table), \
/drivers/clk/sunxi-ng/
Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
48 .table = _table, \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
89 _table, _gate, _flags) \ argument
92 _table), \
106 _table, _flags) \ argument
108 _shift, _width, _table, 0, \
113 _table, _flags) \ argument
116 _table), \
[all …]
Dccu_sdm.h41 #define _SUNXI_CCU_SDM(_table, _enable, \ argument
44 .table = _table, \
45 .table_size = ARRAY_SIZE(_table), \
Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
36 .table = _table, \
49 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
54 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
/drivers/iio/health/
Dafe440x.h117 #define AFE440X_TABLE_ATTR(_name, _table) \ argument
124 for (i = 0; i < ARRAY_SIZE(_table); i++) \
126 _table[i].integer, \
127 _table[i].fract); \
145 #define AFE440X_ATTR(_name, _field, _table) \ argument
151 .val_table = _table, \
152 .table_size = ARRAY_SIZE(_table), \
/drivers/regulator/
D88pm8607.c257 .volt_table = vreg##_table, \
258 .n_voltages = ARRAY_SIZE(vreg##_table), \
260 .vsel_mask = ARRAY_SIZE(vreg##_table) - 1, \
280 .volt_table = LDO##_id##_table, \
281 .n_voltages = ARRAY_SIZE(LDO##_id##_table), \
283 .vsel_mask = (ARRAY_SIZE(LDO##_id##_table) - 1) << (shift), \
Dbcm590xx-regulator.c149 #define BCM590XX_REG_TABLE(_name, _table) \ argument
152 .n_voltages = ARRAY_SIZE(_table), \
153 .volt_table = _table, \
Dpcap-regulator.c218 .n_voltages = ARRAY_SIZE(_vreg##_table), \
219 .volt_table = _vreg##_table, \
Dmax8998.c490 #define MAX8998_CURRENT_REG(_name, _ops, _table, _reg, _mask) \ argument
495 .curr_table = _table, \
496 .n_current_limits = ARRAY_SIZE(_table), \
/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c169 #define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \ argument
172 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
180 .table = lpc18xx_cgu_ ##_table, \
203 #define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \ argument
206 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
210 .table = lpc18xx_cgu_ ##_table, \
269 #define LPC1XX_CGU_CLK_PLL(_id, _table, _pll_ops) \ argument
272 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
277 .table = lpc18xx_cgu_ ##_table, \
Dclk-lpc32xx.c1109 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ argument
1122 .table = (_table), \
1130 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ argument
1141 .table = (_table), \
/drivers/clk/mvebu/
Darmada-37xx-periph.c160 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
163 .table = _table, \
187 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
190 static PERIPH_DIV(_name, _reg, _shift1, _table);
192 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
194 static PERIPH_DIV(_name, _reg, _shift, _table);
/drivers/clk/tegra/
Dclk.h645 _gate_flags, _table, _lock) \ argument
651 .table = _table, \
688 _clk_num, _gate_flags, _clk_id, _table, \ argument
699 _gate_flags, _table, _lock), \
/drivers/clk/
Dclk-bm1880.c144 _div_shift, _div_width, _div_initval, _table, \ argument
155 .table = _table, \
184 _table, _flags) { \ argument
191 .div.table = _table, \
/drivers/clk/microchip/
Dclk-mpfs.c211 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
215 .cfg.table = _table, \
/drivers/clk/at91/
Dsama7g5.c19 #define SAMA7G5_INIT_TABLE(_table, _count) \ argument
23 (_table)[_i] = _i; \
/drivers/clk/stm32/
Dclk-stm32mp13.c288 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
294 .table = (_table),\
/drivers/net/wireless/realtek/rtw89/
Drtw8852a_table.c50952 static const struct rtw89_phy_dig_gain_cfg name##_table = { \