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/drivers/staging/rtl8723bs/include/
Drtw_ht.h81 #define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _… argument
82 #define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1,… argument
86 …ne SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart), 0, 1,… argument
96 …_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3… argument
97 …HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4,… argument
98 …BF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10,… argument
99 …BF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15,… argument
100 …BF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, … argument
Dbasic_types.h39 #define EF1BYTE(_val) \ argument
40 ((u8)(_val))
41 #define EF2BYTE(_val) \ argument
42 (le16_to_cpu(_val))
43 #define EF4BYTE(_val) \ argument
44 (le32_to_cpu(_val))
56 #define WRITEEF1BYTE(_ptr, _val) \ argument
58 (*((u8 *)(_ptr))) = EF1BYTE(_val); \
61 #define WRITEEF2BYTE(_ptr, _val) \ argument
63 (*((u16 *)(_ptr))) = EF2BYTE(_val); \
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/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1413 #define SET_BITS(_var, _index, _width, _val) \ argument
1416 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1422 #define SET_BITS_LE(_var, _index, _width, _val) \ argument
1425 (_var) |= cpu_to_le32((((_val) & \
1442 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ argument
1445 _prefix##_##_field##_WIDTH, (_val))
1452 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ argument
1455 _prefix##_##_field##_WIDTH, (_val))
1472 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1473 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
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/drivers/net/wireless/intel/iwlwifi/
Diwl-csr.h294 #define CSR_HW_REV_STEP_DASH(_val) ((_val) & CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH) argument
295 #define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) argument
298 #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) argument
299 #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) argument
300 #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) argument
301 #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) argument
302 #define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) argument
303 #define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) argument
353 #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF) argument
/drivers/net/wireless/realtek/rtlwifi/
Dbase.h49 #define SET_80211_PS_POLL_AID(_hdr, _val) \ argument
50 (*(u16 *)((u8 *)(_hdr) + 2) = _val)
51 #define SET_80211_PS_POLL_BSSID(_hdr, _val) \ argument
52 ether_addr_copy(((u8 *)(_hdr)) + 4, (u8 *)(_val))
53 #define SET_80211_PS_POLL_TA(_hdr, _val) \ argument
54 ether_addr_copy(((u8 *)(_hdr))+10, (u8 *)(_val))
56 #define SET_80211_HDR_ADDRESS1(_hdr, _val) \ argument
57 CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8 *)(_val))
58 #define SET_80211_HDR_ADDRESS2(_hdr, _val) \ argument
59 CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS2, (u8 *)(_val))
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/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h157 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
159 .val = _val, \
167 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
168 _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
170 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
171 _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
174 #define MPP_FUNCTION(_val, _name, _subname) \ argument
175 MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h198 #define SUNXI_FUNCTION(_val, _name) \ argument
201 .muxval = _val, \
204 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ argument
207 .muxval = _val, \
211 #define SUNXI_FUNCTION_IRQ(_val, _irq) \ argument
214 .muxval = _val, \
218 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ argument
221 .muxval = _val, \
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dfw.h324 #define FW_CMD_IO_UPDATE(rtlpriv, _val) \ argument
325 rtlpriv->rtlhal.fwcmd_iomap = _val;
327 #define FW_CMD_IO_SET(rtlpriv, _val) \ argument
329 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
330 FW_CMD_IO_UPDATE(rtlpriv, _val); \
333 #define FW_CMD_PARA_SET(rtlpriv, _val) \ argument
335 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
336 rtlpriv->rtlhal.fwcmd_ioparam = _val; \
/drivers/virt/geniezone/
Dgzvm_ioeventfd.c62 u64 _val; in gzvm_ioevent_in_range() local
86 _val = *(u8 *)val; in gzvm_ioevent_in_range()
89 _val = *(u16 *)val; in gzvm_ioevent_in_range()
92 _val = *(u32 *)val; in gzvm_ioevent_in_range()
95 _val = *(u64 *)val; in gzvm_ioevent_in_range()
101 return _val == p->datamatch; in gzvm_ioevent_in_range()
/drivers/net/wireless/ath/ath11k/
Ddp.h1252 #define HTT_USR_RATE_PREAMBLE(_val) \ argument
1253 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1254 #define HTT_USR_RATE_BW(_val) \ argument
1255 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1256 #define HTT_USR_RATE_NSS(_val) \ argument
1257 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1258 #define HTT_USR_RATE_MCS(_val) \ argument
1259 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1260 #define HTT_USR_RATE_GI(_val) \ argument
1261 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
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/drivers/media/tuners/
Dmc44s803_priv.h179 #define MC44S803_REG_SM(_val, _reg) \ argument
180 (((_val) << _reg##_S) & (_reg))
183 #define MC44S803_REG_MS(_val, _reg) \ argument
184 (((_val) & (_reg)) >> _reg##_S)
/drivers/gpu/drm/i915/gvt/
Dreg.h96 #define IS_MASKED_BITS_ENABLED(_val, _b) \ argument
97 (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
98 #define IS_MASKED_BITS_DISABLED(_val, _b) \ argument
99 ((_val) & _MASKED_BIT_DISABLE(_b))
/drivers/net/ethernet/synopsys/
Ddwc-xlgmac.h118 typeof(val) _val = (val); \
119 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
120 _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
127 typeof(val) _val = (val); \
128 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
129 _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
/drivers/nvmem/
Dlan9662-otpc.c123 void *_val, size_t bytes) in lan9662_otp_read() argument
126 u8 *val = _val; in lan9662_otp_read()
143 void *_val, size_t bytes) in lan9662_otp_write() argument
146 u8 *val = _val; in lan9662_otp_write()
Duniphier-efuse.c20 unsigned int reg, void *_val, size_t bytes) in uniphier_reg_read() argument
23 u8 *val = _val; in uniphier_reg_read()
Dmtk-efuse.c19 unsigned int reg, void *_val, size_t bytes) in mtk_reg_read() argument
23 u8 *val = _val; in mtk_reg_read()
/drivers/power/supply/
Dmax77650-charger.c64 #define MAX77650_CHARGER_VCHGIN_MIN_SHIFT(_val) ((_val) << 5) argument
67 #define MAX77650_CHARGER_ICHGIN_LIM_SHIFT(_val) ((_val) << 2) argument
/drivers/pinctrl/mediatek/
Dpinctrl-paris.h37 #define MTK_FUNCTION(_val, _name) \ argument
39 .muxval = _val, \
/drivers/iio/proximity/
Dsx9360.c510 static int sx9360_write_thresh(struct sx_common_data *data, int _val) in sx9360_write_thresh() argument
512 unsigned int val = _val; in sx9360_write_thresh()
528 static int sx9360_write_hysteresis(struct sx_common_data *data, int _val) in sx9360_write_hysteresis() argument
530 unsigned int hyst, val = _val; in sx9360_write_hysteresis()
557 static int sx9360_write_far_debounce(struct sx_common_data *data, int _val) in sx9360_write_far_debounce() argument
559 unsigned int regval, val = _val; in sx9360_write_far_debounce()
578 static int sx9360_write_close_debounce(struct sx_common_data *data, int _val) in sx9360_write_close_debounce() argument
580 unsigned int regval, val = _val; in sx9360_write_close_debounce()
Dsx9324.c623 const struct iio_chan_spec *chan, int _val) in sx9324_write_thresh() argument
625 unsigned int reg, val = _val; in sx9324_write_thresh()
644 const struct iio_chan_spec *chan, int _val) in sx9324_write_hysteresis() argument
646 unsigned int hyst, val = _val; in sx9324_write_hysteresis()
673 static int sx9324_write_far_debounce(struct sx_common_data *data, int _val) in sx9324_write_far_debounce() argument
675 unsigned int regval, val = _val; in sx9324_write_far_debounce()
694 static int sx9324_write_close_debounce(struct sx_common_data *data, int _val) in sx9324_write_close_debounce() argument
696 unsigned int regval, val = _val; in sx9324_write_close_debounce()
/drivers/media/i2c/ccs/
Dccs-quirk.h59 #define CCS_MK_QUIRK_REG_8(_reg, _val) \ argument
62 .val = _val, \
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac5.h65 #define SZ_CAP_HBFQ_MASK(_val) ({ typeof(_val) (val) = (_val); \ argument
/drivers/net/wireless/mediatek/mt76/
Ddma.c14 u32 _val; \
16 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \
20 _val = readl(&(_q)->regs->_field); \
21 _val; \
24 #define Q_WRITE(_dev, _q, _field, _val) do { \ argument
29 _val); \
31 writel(_val, &(_q)->regs->_field); \
37 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field) argument
/drivers/clk/meson/
Dvid-pll-div.c33 #define VID_PLL_DIV(_val, _sel, _ft, _fb) \ argument
35 .shift_val = (_val), \
/drivers/gpu/drm/gma500/
Dpsb_drv.h728 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) argument
732 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) argument
734 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) argument

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