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Searched refs:aura (Results 1 – 12 of 12) sorted by relevance

/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_npa.c121 memcpy(ctx, &req->aura, sizeof(struct npa_aura_s)); in rvu_npa_aq_enq_inst()
130 if (req->aura.pool_addr >= pfvf->pool_ctx->qsize) { in rvu_npa_aq_enq_inst()
135 req->aura.pool_addr = pfvf->pool_ctx->iova + in rvu_npa_aq_enq_inst()
136 (req->aura.pool_addr * pfvf->pool_ctx->entry_sz); in rvu_npa_aq_enq_inst()
137 memcpy(ctx, &req->aura, sizeof(struct npa_aura_s)); in rvu_npa_aq_enq_inst()
166 if (req->op == NPA_AQ_INSTOP_INIT && req->aura.ena) in rvu_npa_aq_enq_inst()
169 ena = (req->aura.ena & req->aura_mask.ena) | in rvu_npa_aq_enq_inst()
199 memcpy(&rsp->aura, ctx, in rvu_npa_aq_enq_inst()
230 aq_req.aura.ena = 0; in npa_lf_hwctx_disable()
232 aq_req.aura.bp_ena = 0; in npa_lf_hwctx_disable()
Drvu_debugfs.c1065 struct npa_aura_s *aura = &rsp->aura; in print_npa_aura_ctx() local
1068 seq_printf(m, "W0: Pool addr\t\t%llx\n", aura->pool_addr); in print_npa_aura_ctx()
1071 aura->ena, aura->pool_caching); in print_npa_aura_ctx()
1073 aura->pool_way_mask, aura->avg_con); in print_npa_aura_ctx()
1075 aura->pool_drop_ena, aura->aura_drop_ena); in print_npa_aura_ctx()
1077 aura->bp_ena, aura->aura_drop); in print_npa_aura_ctx()
1079 aura->shift, aura->avg_level); in print_npa_aura_ctx()
1082 (u64)aura->count, aura->nix0_bpid, aura->nix1_bpid); in print_npa_aura_ctx()
1085 (u64)aura->limit, aura->bp, aura->fc_ena); in print_npa_aura_ctx()
1088 seq_printf(m, "W3: fc_be\t\t%d\n", aura->fc_be); in print_npa_aura_ctx()
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Dmbox.h761 struct npa_aura_s aura; member
778 struct npa_aura_s aura; member
/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_common.h351 void (*aura_freeptr)(void *dev, int aura, u64 buf);
696 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, in __cn10k_aura_freeptr() argument
710 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); in __cn10k_aura_freeptr()
728 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) in cn10k_aura_freeptr() argument
736 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); in cn10k_aura_freeptr()
741 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) in otx2_aura_allocptr() argument
744 u64 incr = (u64)aura | BIT_ULL(63); in otx2_aura_allocptr()
750 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) in otx2_aura_freeptr() argument
755 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); in otx2_aura_freeptr()
Dotx2_common.c1291 aq->aura.pool_addr = pool_id; in otx2_aura_init()
1292 aq->aura.pool_caching = 1; in otx2_aura_init()
1293 aq->aura.shift = ilog2(numptrs) - 8; in otx2_aura_init()
1294 aq->aura.count = numptrs; in otx2_aura_init()
1295 aq->aura.limit = numptrs; in otx2_aura_init()
1296 aq->aura.avg_level = 255; in otx2_aura_init()
1297 aq->aura.ena = 1; in otx2_aura_init()
1298 aq->aura.fc_ena = 1; in otx2_aura_init()
1299 aq->aura.fc_addr = pool->fc_addr->iova; in otx2_aura_init()
1300 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ in otx2_aura_init()
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Dotx2_struct.h183 u64 aura : 20; member
Dqos_sq.c199 aura_aq->aura.ena = 0; in otx2_qos_ctx_disable()
Dotx2_dcbnl.c368 npa_aq->aura.nix0_bpid = pfvf->bpid[vlan_prio]; in otx2_update_bpid_in_rqctx()
Dotx2_txrx.c743 sqe_hdr->aura = sq->aura_id; in otx2_sqe_add_hdr()
1360 sqe_hdr->aura = sq->aura_id; in otx2_xdp_sq_append_pkt()
/drivers/crypto/cavium/cpt/
Dcpt_hw_types.h289 u64 aura:12; member
311 u64 aura:12;
/drivers/crypto/marvell/octeontx/
Dotx_cpt_hw_types.h427 u64 aura:12; member
449 u64 aura:12;
/drivers/crypto/cavium/zip/
Dzip_regs.h1264 u64 aura : 12; member
1266 u64 aura : 12;