| /drivers/gpu/drm/radeon/ |
| D | evergreen_cs.c | 177 unsigned bankh; member
269 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; in evergreen_surface_check_2d()
357 switch (surf->bankh) { in evergreen_surface_value_conv_check()
358 case 0: surf->bankh = 1; break; in evergreen_surface_value_conv_check()
359 case 1: surf->bankh = 2; break; in evergreen_surface_value_conv_check()
360 case 2: surf->bankh = 4; break; in evergreen_surface_value_conv_check()
361 case 3: surf->bankh = 8; break; in evergreen_surface_value_conv_check()
364 __func__, __LINE__, prefix, surf->bankh); in evergreen_surface_value_conv_check()
411 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
486 surf.bankw, surf.bankh, in evergreen_cs_track_validate_cb()
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| D | radeon_object.c | 618 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
621 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
635 switch (bankh) { in radeon_bo_set_tiling_flags()
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| D | evergreen.c | 1111 unsigned *bankh, unsigned *mtaspect, in evergreen_tiling_fields() argument
1115 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in evergreen_tiling_fields()
1125 switch (*bankh) { in evergreen_tiling_fields()
1127 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break; in evergreen_tiling_fields()
1128 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break; in evergreen_tiling_fields()
1129 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break; in evergreen_tiling_fields()
1130 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break; in evergreen_tiling_fields()
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| D | atombios_crtc.c | 1147 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1267 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1334 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); in dce4_crtc_do_set_base()
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| D | radeon.h | 356 unsigned *bankh, unsigned *mtaspect,
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_plane.c | 171 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in fill_gfx8_tiling_info_from_flags() local
174 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_gfx8_tiling_info_from_flags()
185 tiling_info->gfx8.bank_height = bankh; in fill_gfx8_tiling_info_from_flags()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v8_0.c | 1910 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1922 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); in dce_v8_0_crtc_do_set_base()
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| D | dce_v6_0.c | 1937 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local
1940 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1949 fb_format |= GRPH_BANK_HEIGHT(bankh); in dce_v6_0_crtc_do_set_base()
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| D | dce_v10_0.c | 1989 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1992 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
2003 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); in dce_v10_0_crtc_do_set_base()
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| D | dce_v11_0.c | 2031 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); in dce_v11_0_crtc_do_set_base()
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