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Searched refs:bus_width (Results 1 – 25 of 120) sorted by relevance

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/drivers/media/platform/rockchip/rkisp1/
Drkisp1-common.c23 .bus_width = 10,
30 .bus_width = 10,
37 .bus_width = 10,
44 .bus_width = 10,
51 .bus_width = 12,
58 .bus_width = 12,
65 .bus_width = 12,
72 .bus_width = 12,
79 .bus_width = 8,
86 .bus_width = 8,
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/drivers/mtd/lpddr/
Dlpddr2_nvm.c76 int bus_width; member
94 static inline u_int build_mr_cfgmask(u_int bus_width) in build_mr_cfgmask() argument
98 if (bus_width == 0x0004) /* x32 device */ in build_mr_cfgmask()
107 static inline u_int build_sr_ok_datamask(u_int bus_width) in build_sr_ok_datamask() argument
111 if (bus_width == 0x0004) /* x32 device */ in build_sr_ok_datamask()
125 val = map->pfow_base + offset*pcm_data->bus_width; in ow_reg_add()
140 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, in ow_enable()
155 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, in ow_disable()
172 u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width); in lpddr2_nvm_do_op()
191 if (pcm_data->bus_width == 0x0004) { /* 2x16 devices stacked */ in lpddr2_nvm_do_op()
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/drivers/memory/
Dmvebu-devbus.c64 u32 bus_width; member
115 err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width); in devbus_get_timing_params()
127 if (r->bus_width == 8) { in devbus_get_timing_params()
128 r->bus_width = 0; in devbus_get_timing_params()
129 } else if (r->bus_width == 16) { in devbus_get_timing_params()
130 r->bus_width = 1; in devbus_get_timing_params()
132 dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width); in devbus_get_timing_params()
215 r->bus_width << ORION_DEV_WIDTH_SHIFT | in devbus_orion_set_timing_params()
236 value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT | in devbus_armada_set_timing_params()
/drivers/mmc/core/
Dmmc.c715 static int mmc_compare_ext_csds(struct mmc_card *card, unsigned bus_width) in mmc_compare_ext_csds() argument
720 if (bus_width == MMC_BUS_WIDTH_1) in mmc_compare_ext_csds()
890 unsigned int bus_width) in __mmc_select_powerclass() argument
902 pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? in __mmc_select_powerclass()
920 pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? in __mmc_select_powerclass()
924 pwrclass_val = (bus_width == EXT_CSD_DDR_BUS_WIDTH_8) ? in __mmc_select_powerclass()
934 if (bus_width & (EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_BUS_WIDTH_8)) in __mmc_select_powerclass()
955 u32 bus_width, ext_csd_bits; in mmc_select_powerclass() local
962 bus_width = host->ios.bus_width; in mmc_select_powerclass()
964 if (bus_width == MMC_BUS_WIDTH_1) in mmc_select_powerclass()
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Dhost.c280 u32 bus_width, drv_type, cd_debounce_delay_ms; in mmc_of_parse() local
287 if (device_property_read_u32(dev, "bus-width", &bus_width) < 0) { in mmc_of_parse()
290 bus_width = 1; in mmc_of_parse()
293 switch (bus_width) { in mmc_of_parse()
304 "Invalid \"bus-width\" value %u!\n", bus_width); in mmc_of_parse()
Dmmc_ops.c680 if (ios->bus_width == MMC_BUS_WIDTH_8) { in mmc_send_tuning()
683 } else if (ios->bus_width == MMC_BUS_WIDTH_4) { in mmc_send_tuning()
840 int mmc_bus_test(struct mmc_card *card, u8 bus_width) in mmc_bus_test() argument
844 if (bus_width == MMC_BUS_WIDTH_8) in mmc_bus_test()
846 else if (bus_width == MMC_BUS_WIDTH_4) in mmc_bus_test()
848 else if (bus_width == MMC_BUS_WIDTH_1) in mmc_bus_test()
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_output.c44 u32 bus_width; in atmel_hlcdc_of_bus_fmt() local
47 ret = of_property_read_u32(ep, "bus-width", &bus_width); in atmel_hlcdc_of_bus_fmt()
53 switch (bus_width) { in atmel_hlcdc_of_bus_fmt()
/drivers/usb/isp1760/
Disp1760-if.c207 u32 bus_width = 0; in isp1760_plat_probe() local
219 of_property_read_u32(dp, "bus-width", &bus_width); in isp1760_plat_probe()
220 if (bus_width == 16) in isp1760_plat_probe()
222 else if (bus_width == 8) in isp1760_plat_probe()
/drivers/dma/
Dimg-mdc-dma.c142 unsigned int bus_width; member
229 if (IS_ALIGNED(dst, mdma->bus_width) && in mdc_list_desc_config()
230 IS_ALIGNED(src, mdma->bus_width)) in mdc_list_desc_config()
231 max_burst = mdma->bus_width * mdma->max_burst_mult; in mdc_list_desc_config()
233 max_burst = mdma->bus_width * (mdma->max_burst_mult - 1); in mdc_list_desc_config()
238 mdc_set_read_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
246 mdc_set_write_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
252 mdc_set_read_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
253 mdc_set_write_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
360 if (width > mchan->mdma->bus_width) in mdc_check_slave_width()
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Dapple-admac.c744 u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) & in admac_device_config() local
750 bus_width |= BUS_WIDTH_8BIT; in admac_device_config()
754 bus_width |= BUS_WIDTH_16BIT; in admac_device_config()
758 bus_width |= BUS_WIDTH_32BIT; in admac_device_config()
775 bus_width |= BUS_WIDTH_FRAME_2_WORDS; in admac_device_config()
778 bus_width |= BUS_WIDTH_FRAME_4_WORDS; in admac_device_config()
784 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no)); in admac_device_config()
/drivers/mmc/host/
Dcavium.c826 int clk_period = 0, power_class = 10, bus_width = 0; in cvm_mmc_set_ios() local
854 switch (ios->bus_width) { in cvm_mmc_set_ios()
856 bus_width = 2; in cvm_mmc_set_ios()
859 bus_width = 1; in cvm_mmc_set_ios()
862 bus_width = 0; in cvm_mmc_set_ios()
867 if (ios->bus_width && ios->timing == MMC_TIMING_MMC_DDR52) in cvm_mmc_set_ios()
868 bus_width |= 4; in cvm_mmc_set_ios()
881 FIELD_PREP(MIO_EMM_SWITCH_BUS_WIDTH, bus_width) | in cvm_mmc_set_ios()
951 u32 id, cmd_skew = 0, dat_skew = 0, bus_width = 0; in cvm_mmc_of_parse() local
985 of_property_read_u32(node, "cavium,bus-max-width", &bus_width); in cvm_mmc_of_parse()
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Dmxs-mmc.c56 unsigned char bus_width; member
380 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | in mxs_mmc_adtc()
499 if (ios->bus_width == MMC_BUS_WIDTH_8) in mxs_mmc_set_ios()
500 host->bus_width = 2; in mxs_mmc_set_ios()
501 else if (ios->bus_width == MMC_BUS_WIDTH_4) in mxs_mmc_set_ios()
502 host->bus_width = 1; in mxs_mmc_set_ios()
504 host->bus_width = 0; in mxs_mmc_set_ios()
Dsdhci-pxav2.c125 u32 bus_width; in pxav2_get_mmc_pdata() local
135 of_property_read_u32(np, "bus-width", &bus_width); in pxav2_get_mmc_pdata()
136 if (bus_width == 8) in pxav2_get_mmc_pdata()
Dsdhci-pltfm.c84 u32 bus_width; in sdhci_get_property() local
90 (device_property_read_u32(dev, "bus-width", &bus_width) == 0 && in sdhci_get_property()
91 bus_width == 1)) in sdhci_get_property()
Dtmio_mmc_core.c168 unsigned char bus_width) in tmio_mmc_set_bus_width() argument
174 if (bus_width == MMC_BUS_WIDTH_1) in tmio_mmc_set_bus_width()
176 else if (bus_width == MMC_BUS_WIDTH_8) in tmio_mmc_set_bus_width()
211 tmio_mmc_set_bus_width(host, host->mmc->ios.bus_width); in tmio_mmc_reset()
733 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4 || in tmio_mmc_start_data()
734 host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) { in tmio_mmc_start_data()
987 tmio_mmc_set_bus_width(host, ios->bus_width); in tmio_mmc_set_ios()
991 tmio_mmc_set_bus_width(host, ios->bus_width); in tmio_mmc_set_ios()
Dmeson-gx-mmc.c599 u32 bus_width, val; in meson_mmc_set_ios() local
639 switch (ios->bus_width) { in meson_mmc_set_ios()
641 bus_width = CFG_BUS_WIDTH_1; in meson_mmc_set_ios()
644 bus_width = CFG_BUS_WIDTH_4; in meson_mmc_set_ios()
647 bus_width = CFG_BUS_WIDTH_8; in meson_mmc_set_ios()
651 ios->bus_width); in meson_mmc_set_ios()
652 bus_width = CFG_BUS_WIDTH_4; in meson_mmc_set_ios()
657 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); in meson_mmc_set_ios()
/drivers/staging/rts5208/
Dsd.c262 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len, argument
294 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
329 u8 bus_width, u8 *buf, int buf_len, int timeout) argument
369 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
943 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width) argument
960 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
1089 u8 func_to_switch, u8 bus_width) argument
1120 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1191 u8 func_group, u8 func_to_switch, u8 bus_width) argument
1204 func_to_switch, bus_width);
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/drivers/spi/
Dspi-synquacer.c135 unsigned int bus_width; member
233 unsigned int speed, mode, bpw, cs, bus_width, transfer_mode; in synquacer_spi_config() local
245 bus_width = xfer->tx_nbits; in synquacer_spi_config()
248 bus_width = xfer->rx_nbits; in synquacer_spi_config()
259 bus_width == sspi->bus_width && bpw == sspi->bpw && in synquacer_spi_config()
341 val |= ((bus_width >> 1) << SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT); in synquacer_spi_config()
348 sspi->bus_width = bus_width; in synquacer_spi_config()
/drivers/media/platform/sunxi/sun6i-csi/
Dsun6i_csi.c46 && v4l2->v4l2_ep.bus.parallel.bus_width == 16) { in sun6i_csi_is_format_supported()
333 unsigned char bus_width; in sun6i_csi_setup_bus() local
343 bus_width = endpoint->bus.parallel.bus_width; in sun6i_csi_setup_bus()
364 cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_YUV422_16BIT : in sun6i_csi_setup_bus()
383 cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_BT1120 : in sun6i_csi_setup_bus()
398 switch (bus_width) { in sun6i_csi_setup_bus()
411 dev_warn(csi_dev->dev, "Unsupported bus width: %u\n", bus_width); in sun6i_csi_setup_bus()
/drivers/staging/greybus/
Dsdio.c594 u8 bus_width; in gb_mmc_set_ios() local
628 switch (ios->bus_width) { in gb_mmc_set_ios()
630 bus_width = GB_SDIO_BUS_WIDTH_1; in gb_mmc_set_ios()
634 bus_width = GB_SDIO_BUS_WIDTH_4; in gb_mmc_set_ios()
637 bus_width = GB_SDIO_BUS_WIDTH_8; in gb_mmc_set_ios()
640 request.bus_width = bus_width; in gb_mmc_set_ios()
/drivers/dma/xilinx/
Dzynqmp_dma.c234 u32 bus_width; member
908 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64; in zynqmp_dma_chan_probe()
911 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width); in zynqmp_dma_chan_probe()
917 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 && in zynqmp_dma_chan_probe()
918 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) { in zynqmp_dma_chan_probe()
1110 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
1111 p->src_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
/drivers/gpu/drm/bridge/
Dti-tfp410.c229 u32 bus_width = 24; in tfp410_parse_timings() local
254 of_property_read_u32(ep, "bus-width", &bus_width); in tfp410_parse_timings()
272 switch (bus_width) { in tfp410_parse_timings()
/drivers/media/platform/samsung/exynos4-is/
Dfimc-reg.c588 u16 bus_width; member
603 u32 bus_width, cfg = 0; in fimc_hw_set_camera_source() local
617 bus_width = pix_desc[i].bus_width; in fimc_hw_set_camera_source()
630 if (bus_width == 8) in fimc_hw_set_camera_source()
632 else if (bus_width == 16) in fimc_hw_set_camera_source()
/drivers/edac/
Dfsl_ddr_edac.c279 u32 bus_width; in fsl_mc_check() local
306 bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) & in fsl_mc_check()
308 if (bus_width == 64) in fsl_mc_check()
331 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { in fsl_mc_check()
/drivers/scsi/aic7xxx/
Daic7xxx_core.c166 u_int bus_width);
170 u_int bus_width, u_int ppr_options);
2396 u_int *bus_width, role_t role) in ahc_validate_width() argument
2398 switch (*bus_width) { in ahc_validate_width()
2402 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; in ahc_validate_width()
2407 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; in ahc_validate_width()
2412 *bus_width = min((u_int)tinfo->user.width, *bus_width); in ahc_validate_width()
2414 *bus_width = min((u_int)tinfo->goal.width, *bus_width); in ahc_validate_width()
3056 u_int bus_width) in ahc_construct_wdtr() argument
3059 ahc->msgout_buf + ahc->msgout_index, bus_width); in ahc_construct_wdtr()
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