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Searched refs:cgu (Results 1 – 16 of 16) sorted by relevance

/drivers/clk/ingenic/
Dcgu.c30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
65 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
72 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
103 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
180 static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu, in ingenic_pll_check_stable() argument
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DMakefile2 obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
3 obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
4 obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
5 obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
6 obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
7 obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
8 obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
9 obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
Djz4780-cgu.c103 static struct ingenic_cgu *cgu; variable
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
186 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_enable()
187 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_enable()
196 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_disable()
197 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_disable()
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Dx1000-cgu.c61 static struct ingenic_cgu *cgu; variable
69 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
121 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
123 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
126 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
128 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
134 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_enable()
135 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_enable()
144 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_disable()
145 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_disable()
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Dx1830-cgu.c55 static struct ingenic_cgu *cgu; variable
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled()
453 cgu = ingenic_cgu_new(x1830_cgu_clocks, in x1830_cgu_init()
455 if (!cgu) { in x1830_cgu_init()
460 retval = ingenic_cgu_register_clocks(cgu); in x1830_cgu_init()
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Djz4770-cgu.c49 static struct ingenic_cgu *cgu; variable
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
448 cgu = ingenic_cgu_new(jz4770_cgu_clocks, in jz4770_cgu_init()
450 if (!cgu) { in jz4770_cgu_init()
455 retval = ingenic_cgu_register_clocks(cgu); in jz4770_cgu_init()
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Djz4725b-cgu.c33 static struct ingenic_cgu *cgu; variable
260 cgu = ingenic_cgu_new(jz4725b_cgu_clocks, in jz4725b_cgu_init()
262 if (!cgu) { in jz4725b_cgu_init()
267 retval = ingenic_cgu_register_clocks(cgu); in jz4725b_cgu_init()
271 ingenic_cgu_register_syscore_ops(cgu); in jz4725b_cgu_init()
Djz4740-cgu.c48 static struct ingenic_cgu *cgu; variable
258 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
260 if (!cgu) { in jz4740_cgu_init()
265 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
269 ingenic_cgu_register_syscore_ops(cgu); in jz4740_cgu_init()
Djz4760-cgu.c425 struct ingenic_cgu *cgu; in jz4760_cgu_init() local
428 cgu = ingenic_cgu_new(jz4760_cgu_clocks, in jz4760_cgu_init()
430 if (!cgu) { in jz4760_cgu_init()
435 retval = ingenic_cgu_register_clocks(cgu); in jz4760_cgu_init()
439 ingenic_cgu_register_syscore_ops(cgu); in jz4760_cgu_init()
Dpm.c39 void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) in ingenic_cgu_register_syscore_ops() argument
42 ingenic_cgu_base = cgu->base; in ingenic_cgu_register_syscore_ops()
Dcgu.h209 struct ingenic_cgu *cgu; member
237 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
Dpm.h10 void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu);
/drivers/clk/x86/
DMakefile4 obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o
/drivers/clk/nxp/
DMakefile2 obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o
/drivers/net/ethernet/intel/ice/
Dice_sbq_cmd.h53 cgu = 0x06 enumerator
Dice_ptp_hw.c676 cgu_msg.dest_dev = cgu; in ice_read_cgu_reg_e822()
708 cgu_msg.dest_dev = cgu; in ice_write_cgu_reg_e822()