Searched refs:clk_hw_set_rate_range (Results 1 – 9 of 9) sorted by relevance
| /drivers/clk/bcm/ |
| D | clk-raspberrypi.c | 320 clk_hw_set_rate_range(&data->hw, min_rate, max_rate); in raspberrypi_clk_register()
334 clk_hw_set_rate_range(&data->hw, variant->min_rate, max_rate); in raspberrypi_clk_register()
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| /drivers/clk/versatile/ |
| D | clk-vexpress-osc.c | 101 clk_hw_set_rate_range(&osc->hw, osc->rate_min, osc->rate_max); in vexpress_osc_probe()
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| /drivers/clk/ |
| D | clk-scmi.c | 165 clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate); in scmi_clk_ops_init()
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| D | clk-scpi.c | 166 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
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| D | clk.c | 723 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, in clk_hw_set_rate_range() function
729 EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
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| D | clk_test.c | 889 clk_hw_set_rate_range(hw, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2); in clk_test_orphan_transparent_multiple_parent_mux_set_range_set_parent_get_rate()
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| /drivers/clk/zynqmp/ |
| D | pll.c | 344 clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX); in zynqmp_clk_register_pll()
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| /drivers/clk/xilinx/ |
| D | xlnx_vcu.c | 429 clk_hw_set_rate_range(hw, pll->fvco_min, pll->fvco_max); in xvcu_register_pll()
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| /drivers/clk/davinci/ |
| D | pll.c | 470 clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate, in davinci_pll_clk_register()
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