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Searched refs:cons_idx (Results 1 – 11 of 11) sorted by relevance

/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_qp.c101 ci_start = atomic_read(&wq->cons_idx); in hinic_sq_prepare_ctxt()
163 ci_start = atomic_read(&wq->cons_idx); in hinic_rq_prepare_ctxt()
713 unsigned int *wqe_size, u16 *cons_idx) in hinic_sq_read_wqebb() argument
722 hw_wqe = hinic_read_wqe(sq->wq, sizeof(*ctrl), cons_idx); in hinic_sq_read_wqebb()
726 *skb = sq->saved_skb[*cons_idx]; in hinic_sq_read_wqebb()
751 unsigned int wqe_size, u16 *cons_idx) in hinic_sq_read_wqe() argument
755 hw_wqe = hinic_read_wqe(sq->wq, wqe_size, cons_idx); in hinic_sq_read_wqe()
756 *skb = sq->saved_skb[*cons_idx]; in hinic_sq_read_wqe()
839 struct sk_buff **skb, u16 *cons_idx) in hinic_rq_read_wqe() argument
846 hw_wqe = hinic_read_wqe(rq->wq, wqe_size, cons_idx); in hinic_rq_read_wqe()
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Dhinic_hw_qp.h195 unsigned int wqe_size, u16 *cons_idx);
199 unsigned int *wqe_size, u16 *cons_idx);
214 struct sk_buff **skb, u16 *cons_idx);
219 u16 *cons_idx);
221 void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
225 u16 cons_idx, struct hinic_sge *sge);
Dhinic_hw_wq.c562 atomic_set(&wq->cons_idx, 0); in hinic_wq_allocate()
666 atomic_set(&wq[i].cons_idx, 0); in hinic_wqs_cmdq_alloc()
808 atomic_add(num_wqebbs, &wq->cons_idx); in hinic_put_wqe()
822 u16 *cons_idx) in hinic_read_wqe() argument
832 curr_cons_idx = atomic_read(&wq->cons_idx); in hinic_read_wqe()
840 *cons_idx = curr_cons_idx; in hinic_read_wqe()
848 copy_wqe_to_shadow(wq, shadow_addr, num_wqebbs, *cons_idx); in hinic_read_wqe()
852 return WQ_PAGE_ADDR(wq, *cons_idx) + WQE_PAGE_OFF(wq, *cons_idx); in hinic_read_wqe()
862 struct hinic_hw_wqe *hinic_read_wqe_direct(struct hinic_wq *wq, u16 cons_idx) in hinic_read_wqe_direct() argument
864 return WQ_PAGE_ADDR(wq, cons_idx) + WQE_PAGE_OFF(wq, cons_idx); in hinic_read_wqe_direct()
Dhinic_hw_wq.h44 atomic_t cons_idx; member
104 u16 *cons_idx);
106 struct hinic_hw_wqe *hinic_read_wqe_direct(struct hinic_wq *wq, u16 cons_idx);
Dhinic_hw_eqs.c58 #define GET_CURR_AEQ_ELEM(eq) GET_AEQ_ELEM(eq, (eq)->cons_idx)
60 #define GET_CURR_CEQ_ELEM(eq) GET_CEQ_ELEM(eq, (eq)->cons_idx)
205 val |= HINIC_EQ_CI_SET(eq->cons_idx, IDX) | in eq_update_ci()
268 eq->cons_idx++; in aeq_irq_handler()
270 if (eq->cons_idx == eq->q_len) { in aeq_irq_handler()
271 eq->cons_idx = 0; in aeq_irq_handler()
332 eq->cons_idx++; in ceq_irq_handler()
334 if (eq->cons_idx == eq->q_len) { in ceq_irq_handler()
335 eq->cons_idx = 0; in ceq_irq_handler()
739 eq->cons_idx = 0; in init_eq()
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Dhinic_hw_api_cmd.c149 chain->cons_idx = get_hw_cons_idx(chain); in chain_busy()
153 if (chain->cons_idx == MASKED_IDX(chain, prod_idx + 1)) { in chain_busy()
155 chain->chain_type, chain->cons_idx, in chain_busy()
310 chain->cons_idx = HINIC_API_CMD_STATUS_GET(status, CONS_IDX); in api_cmd_status_update()
329 if (chain->cons_idx == chain->prod_idx) { in wait_for_status_poll()
824 chain->cons_idx = 0; in api_chain_init()
Dhinic_debugfs.c33 return atomic_read(&wq->cons_idx) & wq->mask; in hinic_dbg_get_sq_info()
63 return atomic_read(&wq->cons_idx) & wq->mask; in hinic_dbg_get_rq_info()
Dhinic_hw_api_cmd.h181 u32 cons_idx; member
Dhinic_hw_cmdq.c597 static void cmdq_sync_cmd_handler(struct hinic_cmdq *cmdq, u16 cons_idx, in cmdq_sync_cmd_handler() argument
600 u16 prod_idx = cons_idx; in cmdq_sync_cmd_handler()
722 HINIC_CMDQ_CTXT_BLOCK_INFO_SET(atomic_read(&wq->cons_idx), CI); in cmdq_init_queue_ctxt()
Dhinic_hw_eqs.h181 u32 cons_idx; member
Dhinic_main.c831 sw_ci = atomic_read(&sq->wq->cons_idx) & sq->wq->mask; in hinic_tx_timeout()